| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 110460
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llvm-svn: 110454
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llvm-svn: 110453
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When a physical register is in use, some alias of that register has a live
interval with a relevant live range. That is the sad state of intervals after
physreg coalescing of subregs, and it is good enough for correct register
allocation.
llvm-svn: 110452
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llvm-svn: 110429
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This pass tries to remove comparison instructions when possible. For instance,
if you have this code:
sub r1, 1
cmp r1, 0
bz L1
and "sub" either sets the same flag as the "cmp" instruction or could be
converted to set the same flag, then we can eliminate the "cmp" instruction all
together. This is a important for ARM where the ALU instructions could set the
CPSR flag, but need a special suffix ('s') to do so.
llvm-svn: 110423
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use location of MBB->end(). If a block does not have terminator then incoming iterator points to end().
llvm-svn: 110411
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llvm-svn: 110410
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When a joined COPY changes subreg liveness, we keep it around as a KILL,
otherwise it is safe to delete.
llvm-svn: 110403
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LiveVariables becomes horribly wrong while the coalescer is running, but the
analysis is not zapped until after the coalescer pass has run. This causes tons
of false reports when calling verify form the coalescer.
llvm-svn: 110402
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address of the static
ID member as the sole unique type identifier. Clean up APIs related to this change.
llvm-svn: 110396
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We verify that the LiveInterval is live at uses and defs, and that all
instructions have a SlotIndex.
Stuff we don't check yet:
- Is the LiveInterval minimal?
- Do all defs correspond to instructions or phis?
- Do all defs dominate all their live ranges?
- Are all live ranges continually reachable from their def?
llvm-svn: 110386
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be killed before being redefined.
These checks are usually disabled, and usually fail when enabled. We de facto
allow live registers to be redefined without a kill, the corresponding
assertions in RegScavenger were removed long ago.
llvm-svn: 110362
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we sometimes compare singular iterators, reported by ENABLE_EXPENSIVE_CHECKS.
This fixes PR7825.
llvm-svn: 110355
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because it could create such things. This fixes a MingW buildbot test failure.
llvm-svn: 110279
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This helps avoid silly code:
%R0<def = LOAD <fi#5>
STORE <fi#5>, %R0<kill>
llvm-svn: 110266
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We are now at a point where we can split around simple single-entry, single-exit
loops, although still with some bugs.
llvm-svn: 110257
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llvm-svn: 110255
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llvm-svn: 110248
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llvm-svn: 110244
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be triggered by valid, if dubious, IR.
llvm-svn: 110240
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used by DBG_VALUE machine instructions or not. If a spilled register is used by DBG_VALUE machine instruction then insert a new DBG_VALUE machine instruction to encode variable's new location on stack.
llvm-svn: 110235
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its location on stack.
llvm-svn: 110234
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llvm-svn: 110183
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When the normalizeSpillWeights function was introduced, I forgot to remove this
normalization.
This change could affect register allocation. Hopefully for the better.
llvm-svn: 110119
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llvm-svn: 110069
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llvm-svn: 110045
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Fixes potential ambiguity problems on VS 2010.
Patch by nobled!
llvm-svn: 110029
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ISD::AND case of TargetLowering::SimplifyDemandedBits.
llvm-svn: 110019
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llvm-svn: 109966
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check the range of the constant when optimizing a comparison between a
constant and a sign_extend_inreg node.
llvm-svn: 109854
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ownership of the TargetAsmBackend and the MCCodeEmitter.
llvm-svn: 109767
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llvm-svn: 109765
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multiple defs, like t2LDRSB_POST.
The first def could accidentally steal the physreg that the second, tied def was
required to be allocated to.
Now, the tied use-def is treated more like an early clobber, and the physreg is
reserved before allocating the other defs.
This would never be a problem when the tied def was the only def which is the
usual case.
This fixes MallocBench/gs for thumb2 -O0.
llvm-svn: 109715
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llvm-svn: 109608
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llvm-svn: 109538
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llvm-svn: 109525
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ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself
recursively and returning a SCALAR_TO_VECTOR node, but assuming the input was always a BUILD_VECTOR.
llvm-svn: 109519
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llvm-svn: 109513
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llvm-svn: 109511
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protectors, to be near the stack protectors on the stack. Accomplish this by
tagging the stack object with a predicate that indicates that it would trigger
this. In the prolog-epilog inserter, assign these objects to the stack after the
stack protector but before the other objects.
llvm-svn: 109481
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rewrite instructions for live range splitting.
Still work in progress.
llvm-svn: 109469
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llvm-svn: 109468
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llvm-svn: 109462
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enough to factor into scheduling priority. Eliminate it and add early exits to speed up scheduling.
llvm-svn: 109449
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llvm-svn: 109415
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llvm-svn: 109402
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parameter)
may be used uninitialized in the callers of HighRegPressure.
llvm-svn: 109393
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llvm-svn: 109388
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llvm-svn: 109383
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