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* Teach DAG combiner to turn a BUILD_VECTOR of UNDEFs into an UNDEF of vector ↵Craig Topper2012-01-171-4/+8
| | | | | | type. llvm-svn: 148297
* misched: Inital interface and implementation for ScheduleTopDownLive and ↵Andrew Trick2012-01-171-17/+130
| | | | | | ShuffleInstructions. llvm-svn: 148291
* Renamed MachineScheduler to ScheduleTopDownLive.Andrew Trick2012-01-174-51/+63
| | | | | | Responding to code review. llvm-svn: 148290
* Moving options declarations around.Andrew Trick2012-01-172-2/+7
| | | | | | More short term hackery until we have a way to configure passes that work on LiveIntervals. llvm-svn: 148289
* Add 148175 back. I am unable to reproduce any non determinism in a dragoneggRafael Espindola2012-01-171-2/+4
| | | | | | | | | | | or clang bootstrap. I will keep an eye on the bots. Original message: Only emit the Leh_func_endN symbol when needed. llvm-svn: 148283
* Changed flag operand of ISD::FP_ROUND to TargetConstant as it should not get ↵Pete Cooper2012-01-171-2/+3
| | | | | | checked for legalisation llvm-svn: 148275
* Fix typo in comment.Lang Hames2012-01-171-1/+1
| | | | llvm-svn: 148268
* Removing unused default switch cases in switches over enums that already ↵David Blaikie2012-01-161-1/+1
| | | | | | | | account for all enumeration values explicitly. (This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them) llvm-svn: 148262
* AggressiveAntiDepBreaker needs to skip debug values because a debug value ↵Hal Finkel2012-01-161-0/+3
| | | | | | does not have a corresponding SUnit llvm-svn: 148260
* Extract method for detecting constant unallocatable physregs.Jakob Stoklund Olesen2012-01-164-41/+21
| | | | | | It is safe to move uses of such registers. llvm-svn: 148259
* Give better scavenger errors by invoking the verifier.Jakob Stoklund Olesen2012-01-161-1/+6
| | | | llvm-svn: 148251
* Add a new kind of MachineOperand: MO_RegisterMask.Jakob Stoklund Olesen2012-01-161-0/+5
| | | | | | | | | | | | | | | | | | | | | Register masks will be used as a compact representation of large clobber lists. Currently, an x86 call instruction has some 40 operands representing call-clobbered registers. That's more than 1kB of useless operands per call site. A register mask operand references a bit mask of call-preserved registers, everything else is clobbered. The bit mask will typically come from TargetRegisterInfo::getCallPreservedMask(). By abandoning ImplicitDefs for call-clobbered registers, it also becomes possible to share call instruction descriptions between calling conventions, and we can get rid of the WINCALL* instructions. This patch introduces the new operand kind. Future patches will add RegMask support to target-independent passes before finally the fixed clobber lists can be removed from call instruction descriptions. llvm-svn: 148250
* Refactor variables unused under non-assert builds (& remove two entirely ↵David Blaikie2012-01-161-2/+0
| | | | | | unused variables). llvm-svn: 148230
* Changed intrinsic ID operand to a target constant as its not used in any ↵Pete Cooper2012-01-161-1/+1
| | | | | | arithmetic so should not be checked in legalisation llvm-svn: 148228
* [AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits.Nadav Rotem2012-01-151-5/+22
| | | | | | | | | | | We know that the blend instructions only use the MSB, so if the mask is sign-extended then we can convert it into a SHL instruction. This is a common pattern because the type-legalizer sign-extends the i1 type which is used by the LLVM-IR for the condition. Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL. llvm-svn: 148225
* Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through ↵Benjamin Kramer2012-01-151-7/+5
| | | | | | CodeGen. llvm-svn: 148218
* DAGCombiner: Deduplicate code.Benjamin Kramer2012-01-151-24/+14
| | | | llvm-svn: 148217
* Truncate of undef is just undef of smaller size.Craig Topper2012-01-151-5/+6
| | | | llvm-svn: 148205
* Speculatively revert commit 148175 (rafael), to see if this fixesDuncan Sands2012-01-141-4/+2
| | | | | | | | non-determinism in the 32 bit dragonegg buildbot. Original commit message: Only emit the Leh_func_endN symbol when needed. llvm-svn: 148191
* Only emit the Leh_func_endN symbol when needed.Rafael Espindola2012-01-141-2/+4
| | | | llvm-svn: 148175
* misched: Initial code for building an MI level scheduling DAGAndrew Trick2012-01-144-21/+113
| | | | llvm-svn: 148174
* Move physreg dependency generation into aptly named addPhysRegDeps.Andrew Trick2012-01-142-155/+182
| | | | llvm-svn: 148173
* misched: Added ScheduleDAGInstrs::IsPostRAAndrew Trick2012-01-144-11/+17
| | | | llvm-svn: 148172
* misched: Invoke the DAG builder on each sequence of schedulable instructions.Andrew Trick2012-01-141-6/+31
| | | | llvm-svn: 148171
* Move things around to make the file navigable, even though it will probably ↵Andrew Trick2012-01-141-19/+32
| | | | | | be split up later. llvm-svn: 148170
* After r147827 and r147902, it's now possible for unallocatable registers to beEvan Cheng2012-01-141-6/+22
| | | | | | | | | | | | | | | | | | | live across BBs before register allocation. This miscompiled 197.parser when a cmp + b are optimized to a cbnz instruction even though the CPSR def is live-in a successor. cbnz r6, LBB89_12 ... LBB89_12: ble LBB89_1 The fix consists of two parts. 1) Teach LiveVariables that some unallocatable registers might be liveouts so don't mark their last use as kill if they are. 2) ARM constantpool island pass shouldn't form cbz / cbnz if the conditional branch does not kill CPSR. rdar://10676853 llvm-svn: 148168
* Remove previous commit while I debug the bot failures.Rafael Espindola2012-01-131-0/+3
| | | | llvm-svn: 148156
* Remove label that is not used anymore.Rafael Espindola2012-01-131-3/+0
| | | | llvm-svn: 148150
* Remove pointless mode line in .cpp file.Andrew Trick2012-01-131-1/+1
| | | | llvm-svn: 148143
* Added the MachineSchedulerPass skeleton.Andrew Trick2012-01-135-0/+241
| | | | llvm-svn: 148105
* wrong filenameAndrew Trick2012-01-131-1/+1
| | | | llvm-svn: 148103
* 80-col violationAndrew Trick2012-01-131-3/+3
| | | | llvm-svn: 148102
* DAGCombine's logic for forming pre- and post- indexed loads / stores were beingEvan Cheng2012-01-131-9/+44
| | | | | | | | | | | | | | | | overly conservative. It was concerned about cases where it would prohibit folding simple [r, c] addressing modes. e.g. ldr r0, [r2] ldr r1, [r2, #4] => ldr r0, [r2], #4 ldr r1, [r2] Change the logic to look for such cases which allows it to form indexed memory ops more aggressively. rdar://10674430 llvm-svn: 148086
* Revert accidental commit.Bill Wendling2012-01-121-65/+0
| | | | llvm-svn: 148065
* Fix the code that was WRONG.Bill Wendling2012-01-121-0/+65
| | | | | | | The registers are placed into the saved registers list in the reverse order, which is why the original loop was written to loop backwards. llvm-svn: 148064
* Added FPOW, FEXP, FLOG to PromoteNode so that custom actions can be set to ↵Pete Cooper2012-01-121-0/+18
| | | | | | | | Promote for those operations. Sorry, no test case yet llvm-svn: 148050
* When hoisting common code, watch out for uses which are marked "kill". If theEvan Cheng2012-01-121-0/+5
| | | | | | | | | | | killed registers are needed below the insertion point, then unset the kill marker. Sorry I'm not able to find a reduced test case. rdar://10660944 llvm-svn: 148043
* Allow targets to select source order pre-RA scheduler.Evan Cheng2012-01-121-1/+2
| | | | llvm-svn: 148033
* Make SplitAnalysis::UseSlots private.Jakob Stoklund Olesen2012-01-122-6/+10
| | | | llvm-svn: 148031
* Make data structures private.Jakob Stoklund Olesen2012-01-113-11/+17
| | | | llvm-svn: 147979
* Sink spillInterferences into RABasic.Jakob Stoklund Olesen2012-01-113-63/+62
| | | | | | This helper method is too simplistic for RAGreedy. llvm-svn: 147976
* Cleanup.Jakob Stoklund Olesen2012-01-111-9/+0
| | | | llvm-svn: 147975
* Move RegAllocBase into its own cpp file separate from RABasic.Jakob Stoklund Olesen2012-01-113-312/+336
| | | | | | No functional change. llvm-svn: 147972
* On AVX, we can load v8i32 at a time. The bug happens when two uneven loads ↵Nadav Rotem2012-01-111-5/+23
| | | | | | | | | | are used. When we load the v12i32 type, the GenWidenVectorLoads method generates two loads: v8i32 and v4i32 and attempts to use CONCAT_VECTORS to join them. In this fix I concat undef values to widen the smaller value. The test "widen_load-2.ll" also exposes this bug on AVX. llvm-svn: 147964
* Teach the X86 instruction selection to do some heroic transforms toChandler Carruth2012-01-111-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | detect a pattern which can be implemented with a small 'shl' embedded in the addressing mode scale. This happens in real code as follows: unsigned x = my_accelerator_table[input >> 11]; Here we have some lookup table that we look into using the high bits of 'input'. Each entity in the table is 4-bytes, which means this implicitly gets turned into (once lowered out of a GEP): *(unsigned*)((char*)my_accelerator_table + ((input >> 11) << 2)); The shift right followed by a shift left is canonicalized to a smaller shift right and masking off the low bits. That hides the shift right which x86 has an addressing mode designed to support. We now detect masks of this form, and produce the longer shift right followed by the proper addressing mode. In addition to saving a (rather large) instruction, this also reduces stalls in Intel chips on benchmarks I've measured. In order for all of this to work, one part of the DAG needs to be canonicalized *still further* than it currently is. This involves removing pointless 'trunc' nodes between a zextload and a zext. Without that, we end up generating spurious masks and hiding the pattern. llvm-svn: 147936
* Detect when a value is undefined on an edge to a landing pad.Jakob Stoklund Olesen2012-01-111-4/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Consider this code: int h() { int x; try { x = f(); g(); } catch (...) { return x+1; } return x; } The variable x is undefined on the first edge to the landing pad, but it has the f() return value on the second edge to the landing pad. SplitAnalysis::getLastSplitPoint() would assume that the return value from f() was live into the landing pad when f() throws, which is of course impossible. Detect these cases, and treat them as if the landing pad wasn't there. This allows spill code to be inserted after the function call to f(). <rdar://problem/10664933> llvm-svn: 147912
* Exclusively use SplitAnalysis::getLastSplitPoint().Jakob Stoklund Olesen2012-01-113-25/+14
| | | | | | | | | Delete the alternative implementation in LiveIntervalAnalysis. These functions computed the same thing, but SplitAnalysis caches the result. llvm-svn: 147911
* Avoid CSE of instructions which define physical registers across MBBs unlessEvan Cheng2012-01-111-4/+12
| | | | | | the physical registers are not allocatable. llvm-svn: 147902
* 80 col violation.Evan Cheng2012-01-101-2/+2
| | | | llvm-svn: 147884
* Add 'llvm_unreachable' to passify GCC's understanding of the constraintsChandler Carruth2012-01-105-0/+5
| | | | | | | | of several newly un-defaulted switches. This also helps optimizers (including LLVM's) recognize that every case is covered, and we should assume as much. llvm-svn: 147861
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