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* Remove several unused variables.Rafael Espindola2013-10-013-7/+2
| | | | | | Patch by Alp Toker. llvm-svn: 191757
* SelectionDAG: Clarify comments from r191600Tom Stellard2013-10-011-2/+2
| | | | llvm-svn: 191724
* Add the DW_AT_GNU_ranges_base attribute if we've emitted any rangesEric Christopher2013-10-011-2/+11
| | | | | | into the debug_ranges section. llvm-svn: 191721
* Update comments.Eric Christopher2013-10-011-2/+2
| | | | llvm-svn: 191720
* The DW_AT_GNU_pubnames/pubtypes attributes are actually formEric Christopher2013-09-302-6/+58
| | | | | | | SEC_OFFSET from the beginning of the section so go ahead and emit a label at the beginning of each one. llvm-svn: 191710
* IfConverter: Use TargetSchedule for instruction latenciesArnold Schwaighofer2013-09-303-9/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For targets that have instruction itineraries this means no change. Targets that move over to the new schedule model will use be able the new schedule module for instruction latencies in the if-converter (the logic is such that if there is no itineary we will use the new sched model for the latencies). Before, we queried "TTI->getInstructionLatency()" for the instruction latency and the extra prediction cost. Now, we query the TargetSchedule abstraction for the instruction latency and TargetInstrInfo for the extra predictation cost. The TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if an itinerary exists, otherwise it will use the new schedule model. ATTENTION: Out of tree targets! (I will also send out an email later to LLVMDev) This means, if your target implements unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost); and returns a value for "PredCost", you now also need to implement unsigned getPredictationCost(const MachineInstr *MI); (if your target uses the IfConversion.cpp pass) radar://15077010 llvm-svn: 191671
* Allocate AtomicSDNode operands in SelectionDAG's allocator to stop leakage.Benjamin Kramer2013-09-291-2/+10
| | | | | | | SDNode destructors are never called. As an optimization use AtomicSDNode's internal storage if we have a small number of operands. llvm-svn: 191636
* Fix spelling intruction -> instruction.Robert Wilhelm2013-09-282-2/+2
| | | | llvm-svn: 191610
* SelectionDAG: Silence unused variable warning on release buildsTom Stellard2013-09-281-0/+1
| | | | llvm-svn: 191604
* SelectionDAG: Improve legalization of SELECT_CC with illegal condition codesTom Stellard2013-09-281-13/+37
| | | | | | | | | | | SelectionDAG will now attempt to inverse an illegal conditon in order to find a legal one and if that doesn't work, it will attempt to swap the operands using the inverted condition. There are no new test cases for this, but a nubmer of the existing R600 tests hit this path. llvm-svn: 191602
* SelectionDAG: Try to expand all condition codes using getCCSwappedOperands()Tom Stellard2013-09-283-18/+33
| | | | | | | | | | | | This is useful for targets like R600, which only support GT, GE, NE, and EQ condition codes as it removes the need to handle unsupported condition codes in target specific code. There are no tests with this commit, but R600 has been updated to take advantage of this new feature, so its existing selectcc tests are now testing the swapped operands path. llvm-svn: 191601
* SelectionDAG: Clean up LegalizeSetCCCondCode() functionTom Stellard2013-09-281-26/+51
| | | | | | | | | | | | | | Interpreting the results of this function is not very intuitive, so I cleaned it up to make it more clear whether or not a SETCC op was legalized and how it was legalized (either by swapping LHS and RHS or replacing with AND/OR). This patch does change functionality in the LHS and RHS swapping case, but unfortunately there are no in-tree tests for this. However, this patch is a prerequisite for R600 to take advantage of the LHS and RHS swapping, so tests will be added in subsequent commits. llvm-svn: 191600
* Unify conditionals and reformat.Eric Christopher2013-09-271-16/+16
| | | | llvm-svn: 191582
* [stackprotector] Refactor the StackProtector pass from a single .cpp file ↵Josh Magee2013-09-271-70/+1
| | | | | | | | | | | | | | into StackProtector.h and StackProtector.cpp. No functionality change. Future patches will add analysis which will be used in other passes (PEI, StackSlot). The end goal is to support ssp-strong stack layout rules. WIP. Differential Revision: http://llvm-reviews.chandlerc.com/D1521 llvm-svn: 191570
* Re-apply the change from r191393 with fix for pr17380.Andrea Di Biagio2013-09-271-0/+20
| | | | | | | | | | This change fixes the problem reported in pr17380 and re-add the dagcombine transformation ensuring that the value types are always legal if the transformation is triggered after Legalization took place. Added the test case from pr17380. llvm-svn: 191509
* Revert r191393 since it caused pr17380.Andrea Di Biagio2013-09-261-20/+0
| | | | llvm-svn: 191438
* [Sparc] Implements exception handling in SPARC with DwarfCFI.Venkatraman Govindaraju2013-09-261-0/+3
| | | | llvm-svn: 191432
* Implements parsing and emitting of .cfi_window_save in MC.Venkatraman Govindaraju2013-09-261-0/+3
| | | | llvm-svn: 191431
* [ARM] Use the load-acquire/store-release instructions optimally in AArch32.Amara Emerson2013-09-261-48/+26
| | | | | | Patch by Artyom Skrobov. llvm-svn: 191428
* Added temp flag -misched-bench for staging in default changes.Andrew Trick2013-09-263-3/+3
| | | | llvm-svn: 191423
* whitespaceAndrew Trick2013-09-261-2/+2
| | | | llvm-svn: 191422
* Teach DAGCombiner how to canonicalize dags according to the ruleAndrea Di Biagio2013-09-251-0/+20
| | | | | | | | | | | | (shl (zext (shr A, X)), X) => (zext (shl (shr A, X), X)). The rule only triggers when there are no other uses of the zext to avoid materializing more instructions. This helps the DAGCombiner understand that the shl/shr sequence can then be converted into an and instruction. llvm-svn: 191393
* Mark the x86 machine model as incomplete. PR17367.Andrew Trick2013-09-251-1/+2
| | | | | | | | | | | | Ideally, the machinel model is added at the time the instructions are defined. But many instructions in X86InstrSSE.td still need a model. Without this workaround the scheduler asserts because x86 already has itinerary classes for these instructions, indicating they should be modeled by the scheduler. Since we use the new machine model for other instructions, it expects a new machine model for these too. llvm-svn: 191391
* [PR16882] Ignore noreturn definitions when setting isPhysRegUsed.Quentin Colombet2013-09-251-3/+39
| | | | | | | | | | | | | | | | | PEI inserts a save/restore sequence for the link register, according to the information it gets from the MachineRegisterInfo. MachineRegisterInfo is populated by the VirtRegMap pass. This pass was not aware of noreturn calls and was registering the definitions of these calls the same way as regular operations. Modify VirtRegPass so that it does not set the isPhysRegUsed information for registers only defined by noreturn calls. The rational is that a noreturn call is the "last instruction" of the program (if it returns the behavior is undefined), so everything that is defined by it cannot be used and will not interfere with anything else. Therefore, it is pointless to account for then. llvm-svn: 191349
* Add missing check to SETCC optimization.Eli Friedman2013-09-241-0/+1
| | | | | | PR17338. llvm-svn: 191337
* Comment typo.Andrew Trick2013-09-241-1/+1
| | | | llvm-svn: 191312
* DAGCombiner: Unify rotate matching for extended and unextended amounts.Benjamin Kramer2013-09-241-79/+57
| | | | | | No functionality change, lots of indentation changes. llvm-svn: 191303
* Initial support for Neon scalar instructions.Jiangning Liu2013-09-241-1/+2
| | | | | | | | | | Patch by Ana Pazos. 1.Added support for v1ix and v1fx types. 2.Added Scalar Pairwise Reduce instructions. 3.Added initial implementation of Scalar Arithmetic instructions. llvm-svn: 191263
* [stackprotector] Allow for copies from vreg -> vreg to be in a terminator ↵Michael Gottesman2013-09-241-6/+26
| | | | | | | | | | | sequence. Sometimes a copy from a vreg -> vreg sneaks into the middle of a terminator sequence. It is safe to slice this into the stack protector success bb. This fixes PR16979. llvm-svn: 191260
* Add namespaces to the list of items that we expose via pubnames.Eric Christopher2013-09-241-0/+1
| | | | llvm-svn: 191257
* Add more external types to the pubtypes table. Expand the asmEric Christopher2013-09-231-1/+1
| | | | | | checking patch until we get full dumping support. llvm-svn: 191239
* Rename IsStatic variable to Linkage in order to be a bit more descriptive.Eric Christopher2013-09-231-3/+3
| | | | llvm-svn: 191236
* Formatting.Eric Christopher2013-09-231-6/+6
| | | | llvm-svn: 191235
* Reformat code with clang-format.Bill Wendling2013-09-231-107/+108
| | | | llvm-svn: 191226
* Handle gnu pubtypes sections:Eric Christopher2013-09-231-5/+11
| | | | | | | | | | | a) Make sure we are emitting the correct section in our section labels when we begin the module. b) Make sure we are emitting the correct pubtypes section in the presence of gnu pubtypes. c) For C++ struct, union, class, and enumeration types are default external. llvm-svn: 191225
* fix typo: than -> thenKay Tiong Khoo2013-09-231-1/+1
| | | | llvm-svn: 191214
* Fixed debug_aranges handling for common symbols.Richard Mitton2013-09-233-5/+20
| | | | | | | | | | The size of common symbols is now tracked correctly, so they can be listed in the arange section without needing knowledge of other following symbols. .comm (and .lcomm) do not indicate to the system assembler any particular section to use, so we have to treat them as having no section. Test case update to account for this. llvm-svn: 191210
* Provide basic type safety for array_pod_sort comparators.Benjamin Kramer2013-09-221-3/+2
| | | | | | | | This makes using array_pod_sort significantly safer. The implementation relies on function pointer casting but that should be safe as we're dealing with void* here. llvm-svn: 191175
* ISelDAG: spot chain cycles involving MachineNodesTim Northover2013-09-221-5/+5
| | | | | | | | | | | | | | | | | Previously, the DAGISel function WalkChainUsers was spotting that it had entered already-selected territory by whether a node was a MachineNode (amongst other things). Since it's fairly common practice to insert MachineNodes during ISelLowering, this was not the correct check. Looking around, it seems that other nodes get their NodeId set to -1 upon selection, so this makes sure the same thing happens to all MachineNodes and uses that characteristic to determine whether we should stop looking for a loop during selection. This should fix PR15840. llvm-svn: 191165
* Revert "SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs ↵Juergen Ributzka2013-09-212-35/+8
| | | | | | | | splitting too." This reverts commit r191130. llvm-svn: 191138
* SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too.Juergen Ributzka2013-09-212-8/+35
| | | | | | | | | | | | | | | | | | The Type Legalizer recognizes that VSELECT needs to be split, because the type is to wide for the given target. The same does not always apply to SETCC, because less space is required to encode the result of a comparison. As a result VSELECT is split and SETCC is unrolled into scalar comparisons. This commit fixes the issue by checking for VSELECT-SETCC patterns in the DAG Combiner. If a matching pattern is found, then the result mask of SETCC is promoted to the expected vector mask for the given target. This mask has usually te same size as the VSELECT return type (except for Intel KNL). Now the type legalizer will split both VSELECT and SETCC. This allows the following X86 DAG Combine code to sucessfully detect the MIN/MAX pattern. This fixes PR16695, PR17002, and <rdar://problem/14594431>. llvm-svn: 191130
* Move emission of the debug string table to early in the debugEric Christopher2013-09-203-22/+46
| | | | | | | info finalization to greatly reduce the number of fixups that the assembler has to handle in order to improve compile time. llvm-svn: 191119
* Migrate addGlobalName to the .cpp file as an intermediate stepEric Christopher2013-09-202-2/+6
| | | | | | to further work. llvm-svn: 191113
* Allow subtarget selection of the default MachineScheduler and document the ↵Andrew Trick2013-09-201-12/+22
| | | | | | | | | | | interface. The global registry is used to allow command line override of the scheduler selection, but does not work well as the normal selection API. For example, the same LLVM process should be able to target multiple targets or subtargets. llvm-svn: 191071
* DebugInfo: GDBIndexEntry*String conversion functions now return const char* ↵David Blaikie2013-09-201-2/+2
| | | | | | | | | for easy llvm::formating This was previously invoking UB by passing a user-defined type to format. Thanks to Jordan Rose for pointing this out. llvm-svn: 191060
* Add braces to suppress Clang's dangling-else warning.David Blaikie2013-09-201-2/+4
| | | | | | These violations were introduced in r191049 llvm-svn: 191059
* Added support for generate DWARF .debug_aranges sections automatically.Richard Mitton2013-09-194-12/+226
| | | | llvm-svn: 191052
* Rename ConvergingScheduler to GenericScheduler.Andrew Trick2013-09-191-63/+63
| | | | | | | | | | This was an experimental scheduler a year ago. It's now used by several subtargets, both in-order and out-of-order, and it is about to be enabled by default for x86 and armv7. It will be the new GenericScheduler for subtargets that don't provide their own SchedulingStrategy. llvm-svn: 191051
* DebugInfo: llvm-dwarfdump support for gnu_pubnames sectionDavid Blaikie2013-09-191-2/+2
| | | | llvm-svn: 191050
* PR16726: extend rol/ror matchingKai Nacke2013-09-191-2/+37
| | | | | | | | | | | | | | | | | | | | | C-like languages promote types like unsigned short to unsigned int before performing an arithmetic operation. Currently the rotate matcher in the DAGCombiner does not consider this situation. This commit extends the DAGCombiner in the way that the pattern (or (shl ([az]ext x), (*ext y)), (srl ([az]ext x), (*ext (sub 32, y)))) is folded into ([az]ext (rotl x, y)) The matching is restricted to aext and zext because in this cases the upper bits are either undefined or known. Test case is included. This fixes PR16726. llvm-svn: 191049
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