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* Fix typos.Bill Wendling2009-06-161-2/+2
| | | | llvm-svn: 73464
* Use MainCU if it is available.Devang Patel2009-06-161-2/+3
| | | | llvm-svn: 73457
* Owen Anderson 2009-06-15: Use a SmallPtrSet here, for speed and to match ↵Owen Anderson2009-06-151-5/+14
| | | | | | | | df_iterator. Owen Anderson 2009-06-15: Remember to clear out our maps to prevent crashing. llvm-svn: 73438
* Change this from an assert to a cerr+exit, since it's diagnosing anDan Gohman2009-06-151-2/+6
| | | | | | unsupported inline asm construct, rather than verifying a code invariant. llvm-svn: 73435
* Gracefully handle imbalanced inline function begin and end markers.Devang Patel2009-06-152-2/+9
| | | | llvm-svn: 73426
* ifcvt should ignore cfg where true and false successors are the same.Evan Cheng2009-06-151-1/+12
| | | | llvm-svn: 73423
* CheckTailCallReturnConstraints is missing a check on theArnold Schwaighofer2009-06-151-1/+5
| | | | | | | | | incomming chain of the RETURN node. The incomming chain must be the outgoing chain of the CALL node. This causes the backend to identify tail calls that are not tail calls. This patch fixes this. llvm-svn: 73387
* Part 1.Evan Cheng2009-06-155-86/+39
| | | | | | | | | | | | | | | | | | | | | - Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. llvm-svn: 73381
* Fix old-style type names in comments.Dan Gohman2009-06-141-1/+1
| | | | llvm-svn: 73362
* Move register allocation preference (or hint) from LiveInterval to ↵Evan Cheng2009-06-148-37/+142
| | | | | | MachineRegisterInfo. This allows more passes to set them. llvm-svn: 73346
* Introduce new BinaryObject (blob) class, ELF Writer modified to use it. ↵Bruno Cardoso Lopes2009-06-144-257/+182
| | | | | | BinaryObject.h by Aaron Gray llvm-svn: 73333
* Add a ARM specific pre-allocation pass that re-schedule loads / stores fromEvan Cheng2009-06-131-1/+1
| | | | | | | | | | | consecutive addresses togther. This makes it easier for the post-allocation pass to form ldm / stm. This is step 1. We are still missing a lot of ldm / stm opportunities because of register allocation are not done in the desired order. More enhancements coming. llvm-svn: 73291
* llvm.dbg.region.end() intrinsic is not required to be in _last_ basic block ↵Devang Patel2009-06-131-1/+5
| | | | | | | | in a function. If that happens then any basic block that follows (lexically) the block with regin.end will not have scope info available. LexicalScopeStack relies on processing basic block in CFG order, but this processing order is not guaranteed. Things get complicated when the optimizer gets a chance to optimizer IR with dbg intrinsics. Apply defensive patch to preserve at least one lexical scope till the end of function. llvm-svn: 73282
* Improve style.Owen Anderson2009-06-121-16/+16
| | | | llvm-svn: 73258
* This is supposed to be a preorder numbering of the dominator tree, not the CFG.Owen Anderson2009-06-121-4/+5
| | | | llvm-svn: 73257
* Now with less iterator invalidation, and other forms of crashing!Owen Anderson2009-06-121-3/+6
| | | | llvm-svn: 73256
* If killed register is defined by implicit_def, do not clear it since it's ↵Evan Cheng2009-06-121-5/+12
| | | | | | live range may overlap another def of same register. llvm-svn: 73255
* Clear AbstractInstanceRootMap at the end of the function.Devang Patel2009-06-121-0/+1
| | | | llvm-svn: 73244
* Support for ELF VisibilityBruno Cardoso Lopes2009-06-114-93/+295
| | | | | | | | Emission for globals, using the correct data sections Function alignment can be computed for each target using TargetELFWriterInfo Some small fixes llvm-svn: 73201
* CMake: Updated list of files on lib/CodeGen/CMakeLists.txt.Oscar Fuentes2009-06-101-0/+1
| | | | llvm-svn: 73174
* Remove warnings: no newline at end of file.Sanjiv Gupta2009-06-101-1/+2
| | | | llvm-svn: 73156
* Add the beginnings of an implementatation of lazy liveness analysis, based ↵Owen Anderson2009-06-091-0/+153
| | | | | | | | on "Fast Liveness Checking for SSA-form Programs" by Boissinot, et al. This is still very early, hasn't been tested, and is not yet well documented. More to come soon. llvm-svn: 73141
* Delete comment and fix typoBruno Cardoso Lopes2009-06-072-2/+1
| | | | llvm-svn: 73040
* Fix wrong elf class and byte order initializations.Bruno Cardoso Lopes2009-06-071-2/+2
| | | | llvm-svn: 73039
* Simple ELF32/64 binary files can now be emitted for x86 and x86_64 withoutBruno Cardoso Lopes2009-06-075-59/+162
| | | | | | relocation sections. llvm-svn: 73038
* Tweak the expansion code for BIT_CONVERT to generate better code Eli Friedman2009-06-071-0/+20
| | | | | | converting from an MMX vector to an i64. llvm-svn: 73024
* Slightly generalize the code that handles shuffles of consecutive loads Eli Friedman2009-06-071-78/+37
| | | | | | | | | | | on x86 to handle more cases. Fix a bug in said code that would cause it to read past the end of an object. Rewrite the code in SelectionDAGLegalize::ExpandBUILD_VECTOR to be a bit more general. Remove PerformBuildVectorCombine, which is no longer necessary with these changes. In addition to simplifying the code, with this change, we can now catch a few more cases of consecutive loads. llvm-svn: 73012
* Fix the expansion for CONCAT_VECTORS so that it doesn't create illegal Eli Friedman2009-06-061-17/+1
| | | | | | types. llvm-svn: 72993
* Factor out a couple of helpers.Eli Friedman2009-06-061-78/+101
| | | | llvm-svn: 72992
* Remove elf specific info from ELFWriter.h to Elf.h. Code cleanup and more ↵Bruno Cardoso Lopes2009-06-065-116/+245
| | | | | | comments added llvm-svn: 72982
* Make SINT_TO_FP/UINT_TO_FP vector legalization queries query on the Eli Friedman2009-06-061-3/+7
| | | | | | | integer type to be consistent with normal operation legalization. No visible change because nothing is actually using this at the moment. llvm-svn: 72980
* Add new function attribute - noimplicitfloatDevang Patel2009-06-051-1/+1
| | | | | | | Update code generator to use this attribute and remove NoImplicitFloat target option. Update llc to set this attribute when -no-implicit-float command line option is used. llvm-svn: 72959
* Adapt the x86 build_vector dagcombine to the current state of the legalizer.Nate Begeman2009-06-052-16/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | build vectors with i64 elements will only appear on 32b x86 before legalize. Since vector widening occurs during legalize, and produces i64 build_vector elements, the dag combiner is never run on these before legalize splits them into 32b elements. Teach the build_vector dag combine in x86 back end to recognize consecutive loads producing the low part of the vector. Convert the two uses of TLI's consecutive load recognizer to pass LoadSDNodes since that was required implicitly. Add a testcase for the transform. Old: subl $28, %esp movl 32(%esp), %eax movl 4(%eax), %ecx movl %ecx, 4(%esp) movl (%eax), %eax movl %eax, (%esp) movaps (%esp), %xmm0 pmovzxwd %xmm0, %xmm0 movl 36(%esp), %eax movaps %xmm0, (%eax) addl $28, %esp ret New: movl 4(%esp), %eax pmovzxwd (%eax), %xmm0 movl 8(%esp), %eax movaps %xmm0, (%eax) ret llvm-svn: 72957
* Remove some unnecessary #includes.Dan Gohman2009-06-053-3/+0
| | | | llvm-svn: 72948
* Allow libcalls for i16 sdiv/udiv/rem operations.Sanjiv Gupta2009-06-051-4/+12
| | | | llvm-svn: 72941
* ELF Code Emitter now uses CurBufferPtr, BufferBegin and BufferEnd, as do JIT andBruno Cardoso Lopes2009-06-053-32/+57
| | | | | | | MachO Writer. This will change with the arrival of ObjectCodeEmitter and BinaryObject llvm-svn: 72906
* Split the Add, Sub, and Mul instruction opcodes into separateDan Gohman2009-06-043-47/+32
| | | | | | | | | | | | | | | integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
* Fix FP_TO_UINT->i32 on ppc32 -mcpu=g5. This wasDale Johannesen2009-06-041-6/+5
| | | | | | | | | | | | | | using Promote which won't work because i64 isn't a legal type. It's easy enough to use Custom, but then we have the problem that when the type legalizer is promoting FP_TO_UINT->i16, it has no way of telling it should prefer FP_TO_SINT->i32 to FP_TO_UINT->i32. I have uncomfortably hacked this by making the type legalizer choose FP_TO_SINT when both are Custom. This fixes several regressions in the testsuite. llvm-svn: 72891
* RALinScan::attemptTrivialCoalescing() was returning a virtual register ↵Evan Cheng2009-06-041-3/+9
| | | | | | instead of the physical register it is allocated to. This resulted in virtual register(s) being added the live-in sets. llvm-svn: 72890
* A value defined by an implicit_def can be liven to a use BB. This is ↵Evan Cheng2009-06-041-0/+18
| | | | | | unfortunate. But register allocator still has to add it to the live-in set of the use BB. llvm-svn: 72889
* Removed SimpleRewriter.Lang Hames2009-06-041-82/+2
| | | | llvm-svn: 72880
* Don't do the X * 0.0 -> 0.0 transformation in instcombine, becauseDan Gohman2009-06-042-5/+11
| | | | | | | | instcombine doesn't know when it's safe. To partially compensate for this, introduce new code to do this transformation in dagcombine, which can use UnsafeFPMath. llvm-svn: 72872
* Fix comments.Dan Gohman2009-06-041-2/+2
| | | | llvm-svn: 72870
* Remove a #include of <iostream>.Dan Gohman2009-06-041-1/+0
| | | | llvm-svn: 72828
* Removed more testing code that snuck in earlier.Lang Hames2009-06-041-20/+2
| | | | llvm-svn: 72825
* Move ELFCodeEmiter stuff to new filesBruno Cardoso Lopes2009-06-034-140/+184
| | | | llvm-svn: 72785
* CMake: Added missing source file to lib/CodeGen/CMakeLists.txt.Oscar Fuentes2009-06-031-0/+1
| | | | llvm-svn: 72775
* Fix for PR4225: When rewriter reuse a value in a physical register , it ↵Evan Cheng2009-06-031-5/+19
| | | | | | clear the register kill operand marker and its kill ops information. However, the cleared operand may be a def of a super-register. Clear the kill ops info for the super-register's sub-registers as well. llvm-svn: 72758
* If there is a def of a super-register followed by a use of a sub-register, ↵Evan Cheng2009-06-031-14/+0
| | | | | | | | | | | | | | do *not* add an implicit def of the sub-register. e.g. EAX = ..., AX<imp-def> ... = AX This creates a double-def. Apparently this used to be necessary but is no longer needed. Thanks to Anton for pointing this out. Anton, I cannot create a test case without your uncommitted ARM patches. Please check in a test case for me. llvm-svn: 72755
* Move structures and classes into header files, providing two new headers andBruno Cardoso Lopes2009-06-035-772/+900
| | | | | | | | one new .cpp file, in preparation for merging in the Direct Object Emission changes we're working on. No functional changes. Fixed coding style issues on the original patch. Patch by Aaron Gray llvm-svn: 72754
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