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* Remove trailing whitespacStephen Lin2013-07-101-2/+2
| | | | llvm-svn: 186032
* Use the appropriate unsigned int type for the offset.Adrian Prantl2013-07-101-2/+3
| | | | llvm-svn: 186015
* Safeguard DBG_VALUE handling. Unbreaks the ASAN buildbot.Adrian Prantl2013-07-101-1/+2
| | | | llvm-svn: 186014
* Un-break the buildbot by tweaking the indirection flag.Adrian Prantl2013-07-101-2/+8
| | | | | | Pulled in a testcase from the debuginfo-test suite. llvm-svn: 185993
* Document a known limitation of the status quo.Adrian Prantl2013-07-101-1/+3
| | | | llvm-svn: 185992
* Fix comment.Eric Christopher2013-07-091-1/+1
| | | | llvm-svn: 185984
* Typo.Adrian Prantl2013-07-091-1/+1
| | | | llvm-svn: 185971
* Reapply an improved version of r180816/180817.Adrian Prantl2013-07-099-47/+75
| | | | | | | | | | | | | | | Change the informal convention of DBG_VALUE machine instructions so that we can express a register-indirect address with an offset of 0. The old convention was that a DBG_VALUE is a register-indirect value if the offset (operand 1) is nonzero. The new convention is that a DBG_VALUE is register-indirect if the first operand is a register and the second operand is an immediate. For plain register values the combination reg, reg is used. MachineInstrBuilder::BuildMI knows how to build the new DBG_VALUES. rdar://problem/13658587 llvm-svn: 185966
* WidenVecRes_BUILD_VECTOR must use the first operand's typeHal Finkel2013-07-091-1/+4
| | | | | | | | | | | Because integer BUILD_VECTOR operands may have a larger type than the result's vector element type, and all operands must have the same type, when widening a BUILD_VECTOR node by adding UNDEFs, we cannot use the vector element type, but rather must use the type of the existing operands. Another bug found by llvm-stress. llvm-svn: 185960
* AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and allStephen Lin2013-07-092-5/+5
| | | | | | | | | | | | | | | | | | | | | | | in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in order to resolve the following issues with fmuladd (i.e. optional FMA) intrinsics: 1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd intrinsics even if the subtarget does not support FMA instructions, leading to laughably bad code generation in some situations. 2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128, resulting in a call to a software fp128 FMA implementation. 3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize, etc. to types that support hardware FMAs. The function has also been slightly renamed for consistency and to force a merge/build conflict for any out-of-tree target implementing it. To resolve, see comments and fixed in-tree examples. llvm-svn: 185956
* DAGCombine tryFoldToZero cannot create illegal types after type legalizationHal Finkel2013-07-091-4/+11
| | | | | | | | | | | When folding sub x, x (and other similar constructs), where x is a vector, the result is a vector of zeros. After type legalization, make sure that the input zero elements have a legal type. This type may be larger than the result's vector element type. This was another bug found by llvm-stress. llvm-svn: 185949
* Revert r185872 - "Stop emitting weak symbols into the "coal" sections"Alexander Potapenko2013-07-091-6/+6
| | | | | | | | | | | | | This patch broke `make check-asan` on Mac, causing ld warnings like the following one: ld: warning: direct access in __GLOBAL__I_a to global weak symbol ___asan_mapping_scale means the weak symbol cannot be overridden at runtime. This was likely caused by different translation units being compiled with different visibility settings. The resulting test binaries crashed with incorrect ASan warnings. llvm-svn: 185923
* Style fixes: remove unnecessary braces for one-statement if blocks, no else ↵Stephen Lin2013-07-091-54/+30
| | | | | | after return, etc. No funcionality change. llvm-svn: 185893
* Stop emitting weak symbols into the "coal" sections.Bill Wendling2013-07-081-6/+6
| | | | | | | | | | | | | | | | | The Mach-O linker has been able to support the weak-def bit on any symbol for quite a while now. The compiler however continued to place these symbols into a "coal" section, which required the linker to map them back to the base section name. Replace the sections like this: __TEXT/__textcoal_nt instead use __TEXT/__text __TEXT/__const_coal instead use __TEXT/__const __DATA/__datacoal_nt instead use __DATA/__data <rdar://problem/14265330> llvm-svn: 185872
* Update comment to avoid mentioning DbgValues which is an instanceEric Christopher2013-07-081-1/+1
| | | | | | variable later in the class. llvm-svn: 185866
* Debug Info: clean up usage of Verify.Manman Ren2013-07-083-20/+20
| | | | | | | No functionality change. It should suffice to check the type of a debug info metadata, instead of calling Verify. llvm-svn: 185847
* DebugInfo: Correct comment & re-format a nearby loopDavid Blaikie2013-07-081-5/+3
| | | | llvm-svn: 185844
* DebugInfo: Simplify Address Pool index handling.David Blaikie2013-07-081-5/+3
| | | | | | | | | | Since the pool indexes are necessarily sequential and contiguous, just insert things in the right place rather than having to sort the sequence after the fact. No functionality change. llvm-svn: 185842
* Improve the comment from r185794 (re: PromoteIntRes_BUILD_VECTOR)Hal Finkel2013-07-081-2/+4
| | | | | | | In response to Duncan's review, I believe that the original comment was not as clear as it could be. Hopefully, this is better. llvm-svn: 185824
* Fix PromoteIntRes_BUILD_VECTOR crash with i1 vectorsHal Finkel2013-07-081-1/+7
| | | | | | | | | | | | | This fixes a bug (found by llvm-stress) in DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR where it assumed that the result type would always be larger than the original operands. This is not always true, however, with boolean vectors. For example, promoting a node of type v8i1 (where the operands will be of type i32, the type to which i1 is promoted) will yield a node with a result vector element type of i16 (and operands of type i32). As a result, we cannot blindly assume that we can ANY_EXTEND the operands to the result type. llvm-svn: 185794
* Revert: Emit personality function and Dwarf EH data for Win64 SEH.Kai Nacke2013-07-081-3/+9
| | | | llvm-svn: 185788
* Add the nearbyint -> FNEARBYINT mapping to BasicTargetTransformInfoHal Finkel2013-07-081-0/+2
| | | | | | | | This fixes an oversight that Intrinsic::nearbyint was not being mapped to ISD::FNEARBYINT (thus fixing the over-optimistic cost we were assigning to nearbyint calls for some targets). llvm-svn: 185783
* Remove trailing whitespace from SelectionDAG/*.cppStephen Lin2013-07-0810-60/+60
| | | | llvm-svn: 185780
* SelectionDAGBuilder: style fixes (add space between end parentheses and open ↵Stephen Lin2013-07-061-10/+10
| | | | | | brace) llvm-svn: 185768
* Emit personality function and Dwarf EH data for Win64 SEH.Kai Nacke2013-07-061-9/+3
| | | | | | | | | | | Obviously the personality function should be emitted as language handler instead of the hard coded _GCC_specific_handler. The language specific data must be placed after the unwind information therefore it must not be emitted into a separate section. Reviewed by Charles Davis and Nico Rieck. llvm-svn: 185761
* DAGCombiner: Don't drop extension behavior when shrinking a load when unsafe.Benjamin Kramer2013-07-061-0/+7
| | | | | | | | | | | | ReduceLoadWidth unconditionally drops extensions from loads. Limit it to the case when all of the bits the extension would otherwise produce are dropped by the shrink. It would be possible to shrink the load in more cases by merging the extensions, but this isn't trivial and a very rare case. I left a TODO for that case. Fixes PR16551. llvm-svn: 185755
* Stop putting operations after a tail call.Tim Northover2013-07-061-0/+4
| | | | | | | | This prevents the emission of DAG-generated vreg definitions after a tail call be dropping them entirely (on the grounds that nothing could use them anyway, and they interfere with O0 CodeGen). llvm-svn: 185754
* MC: Implement COFF .linkonce directiveNico Rieck2013-07-061-3/+3
| | | | llvm-svn: 185753
* Use modern API to avoid exposing LiveInterval internals.Jakob Stoklund Olesen2013-07-051-5/+3
| | | | | | No functional change intended. llvm-svn: 185733
* Remove dead function.Jakob Stoklund Olesen2013-07-051-26/+0
| | | | llvm-svn: 185731
* [SystemZ] Remove no-op MVCsRichard Sandiford2013-07-051-1/+10
| | | | | | | | | | | The stack coloring pass has code to delete stores and loads that become trivially dead after coloring. Extend it to cope with single instructions that copy from one frame index to another. The testcase happens to show an example of this kicking in at the moment. It did occur in Real Code too though. llvm-svn: 185705
* Fix double renaming bug in stack coloring passRichard Sandiford2013-07-051-26/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The stack coloring pass renumbered frame indexes with a loop of the form: for each frame index FI for each instruction I that uses FI for each use of FI in I rename FI to FI' This caused problems if an instruction used two frame indexes F0 and F1 and if F0 was renamed to F1 and F1 to F2. The first time we visited the instruction we changed F0 to F1, then we changed both F1s to F2. In other words, the problem was that SSRefs recorded which instructions used an FI, but not which MachineOperands and MachineMemOperands within that instruction used it. This is easily fixed for MachineOperands by walking the instructions once and processing each operand in turn. There's already a loop to do that for dead store elimination, so it seemed more efficient to fuse the two at the block level. MachineMemOperands are more tricky because they can be shared between instructions. The patch handles them by making SSRefs an array of MachineMemOperands rather than an array of MachineInstrs. We might end up processing the same MachineMemOperand twice, but that's OK because we always know from the SSRefs index what the original frame index was. llvm-svn: 185703
* [SystemZ] Clean up register scavenging codeRichard Sandiford2013-07-051-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | SystemZ wants normal register scavenging slots, as close to the stack or frame pointer as possible. The only reason it was using custom code was because PrologEpilogInserter assumed an x86-like layout, where the frame pointer is at the opposite end of the frame from the stack pointer. This meant that when frame pointer elimination was disabled, the slots ended up being as close as possible to the incoming stack pointer, which is the opposite of what we want on SystemZ. This patch adds a new knob to say which layout is used and converts SystemZ to use target-independent scavenging slots. It's one of the pieces needed to support frame-to-frame MVCs, where two slots might be required. The ABI requires us to allocate 160 bytes for calls, so one approach would be to use that area as temporary spill space instead. It would need some surgery to make sure that the slot isn't live across a call though. I stuck to the "isFPCloseToIncomingSP - ..." style comment on the "do what the surrounding code does" principle. The FP case is already covered by several Systemz/frame-* tests, which fail without the PrologueEpilogueInserter change, so no new ones are needed. No behavioural change intended. llvm-svn: 185696
* Simplify code. No functionality change.Benjamin Kramer2013-07-051-7/+3
| | | | llvm-svn: 185689
* Initialize object file info before output streamerNico Rieck2013-07-041-2/+2
| | | | | | | | | r179494 switched to using the object file info to retrieve the default text section for some MC streamers. It is possible that initializing an MC streamer can request sections before the object file info is initialized when the AutoInitSections flag is set on the streamer. llvm-svn: 185670
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-042-19/+0
| | | | | | These exception-related opcodes are not used any longer. llvm-svn: 185625
* Typo.Jakob Stoklund Olesen2013-07-041-1/+1
| | | | llvm-svn: 185618
* Simplify landing pad lowering.Jakob Stoklund Olesen2013-07-042-26/+21
| | | | | | | | | | | | | | | | | | | | | Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering landing pad arguments. These nodes were previously legalized into CopyFromReg nodes, but that never worked properly because the CopyFromReg node weren't guaranteed to be scheduled at the top of the basic block. This meant the exception pointer and selector registers could be clobbered before being copied to a virtual register. This patch copies the two physical registers to virtual registers at the beginning of the basic block, and lowers the landingpad instruction directly to two CopyFromReg nodes reading the *virtual* registers. This is safe because virtual registers don't get clobbered. A future patch will remove the ISD::EXCEPTIONADDR and ISD::EHSELECTION nodes. llvm-svn: 185617
* FastISel can only apend to basic blocks.Jakob Stoklund Olesen2013-07-041-8/+5
| | | | | | | | | | Compute the insertion point from the end of the basic block instead of skipping labels from the front. This caused failures in landing pads when live-in copies where inserted before instruction selection. llvm-svn: 185616
* Live-in copies go *after* EH_LABELs.Jakob Stoklund Olesen2013-07-041-1/+1
| | | | | | This will soon be tested by exception handling working at all. llvm-svn: 185615
* Revert r185595-185596 which broke buildbots.Jakob Stoklund Olesen2013-07-044-21/+45
| | | | | | | Revert "Simplify landing pad lowering." Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes." llvm-svn: 185600
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-032-19/+0
| | | | | | These exception-related opcodes are not used any longer. llvm-svn: 185596
* Simplify landing pad lowering.Jakob Stoklund Olesen2013-07-032-26/+21
| | | | | | | | | | | | | | | | | | | | | Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering landing pad arguments. These nodes were previously legalized into CopyFromReg nodes, but that never worked properly because the CopyFromReg node weren't guaranteed to be scheduled at the top of the basic block. This meant the exception pointer and selector registers could be clobbered before being copied to a virtual register. This patch copies the two physical registers to virtual registers at the beginning of the basic block, and lowers the landingpad instruction directly to two CopyFromReg nodes reading the *virtual* registers. This is safe because virtual registers don't get clobbered. A future patch will remove the ISD::EXCEPTIONADDR and ISD::EHSELECTION nodes. llvm-svn: 185595
* Add MachineBasicBlock::addLiveIn().Jakob Stoklund Olesen2013-07-031-0/+33
| | | | | | | This function adds a live-in physical register to an MBB and ensures that it is copied to a virtual register immediately. llvm-svn: 185594
* Hoist all of the Entry.getLoc() calls int a single variable.Eric Christopher2013-07-031-7/+8
| | | | llvm-svn: 185589
* Make DotDebugLocEntry a class, reorder the members along with commentsEric Christopher2013-07-032-14/+29
| | | | | | for them and update all uses. llvm-svn: 185588
* Elaborate on comment.Eric Christopher2013-07-031-1/+1
| | | | llvm-svn: 185586
* Add names to the header file since they help in documenting the APIEric Christopher2013-07-031-10/+11
| | | | | | (and for consistency). llvm-svn: 185585
* Move typedefs inside the class that they belong to.Eric Christopher2013-07-031-10/+7
| | | | llvm-svn: 185573
* Remove unused field.Eric Christopher2013-07-031-12/+19
| | | | llvm-svn: 185523
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