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* MI-Sched: DEBUG formatting.Andrew Trick2013-04-131-14/+22
| | | | llvm-svn: 179452
* MI-Sched cleanup. If an instruction has no valid sched class, do not attempt ↵Andrew Trick2013-04-131-0/+2
| | | | | | to check for a variant. llvm-svn: 179451
* MI-Sched: schedule physreg copies.Andrew Trick2013-04-132-1/+76
| | | | | | | | | | | The register allocator expects minimal physreg live ranges. Schedule physreg copies accordingly. This is slightly tricky when they occur in the middle of the scheduling region. For now, this is handled by rescheduling the copy when its associated instruction is scheduled. Eventually we may instead bundle them, but only if we can preserve the bundles as parallel copies during regalloc. llvm-svn: 179449
* CostModel: increase the default cost of supported floating point operations ↵Nadav Rotem2013-04-121-4/+7
| | | | | | from 1 to two. Fixed a few tests that changes because now the cost of one insert + a vector operation on two doubles is lower than two scalar operations on doubles. llvm-svn: 179413
* Revert broken pieces of r179373.Benjamin Kramer2013-04-121-16/+16
| | | | | | You can't copy an OwningPtr, and move semantics aren't available in C++98. llvm-svn: 179374
* Replace uses of the deprecated std::auto_ptr with OwningPtr.Andy Gibbs2013-04-123-20/+20
| | | | llvm-svn: 179373
* Don't disable block layout when forcing block alignment.Nadav Rotem2013-04-121-8/+6
| | | | llvm-svn: 179355
* Add a flag to align all basic blocks in the function.Nadav Rotem2013-04-121-0/+14
| | | | | | | | | | When debugging performance regressions we often ask ourselves if the regression that we see is due to poor isel/sched/ra or due to some micro-architetural problem. When comparing two code sequences one good way to rule out front-end bottlenecks (and other the issues) is to force code alignment. This pass adds a flag that forces the alignment of all of the basic blocks in the program. llvm-svn: 179353
* Add braces around || in && to pacify GCC.Benjamin Kramer2013-04-111-4/+4
| | | | llvm-svn: 179275
* Manually remove successors in if conversion when CopyAndPredicateBlock is usedHal Finkel2013-04-101-0/+8
| | | | | | | | | | | | | | | In the simple and triangle if-conversion cases, when CopyAndPredicateBlock is used because the to-be-predicated block has other predecessors, we need to explicitly remove the old copied block from the successors list. Normally if conversion relies on TII->AnalyzeBranch combined with BB->CorrectExtraCFGEdges to cleanup the successors list, but if the predicated block contained an un-analyzable branch (such as a now-predicated return), then this will fail. These extra successors were causing a problem on PPC because it was causing later passes (such as PPCEarlyReturm) to leave dead return-only basic blocks in the code. llvm-svn: 179227
* Generalize the PassConfig API and remove addFinalizeRegAlloc().Andrew Trick2013-04-101-36/+50
| | | | | | | | | | The target hooks are getting out of hand. What does it mean to run before or after regalloc anyway? Allowing either Pass* or AnalysisID pass identification should make it much easier for targets to use the substitutePass and insertPass APIs, and create less need for badly named target hooks. llvm-svn: 179140
* The .dwo section shouldn't contain the unrelocated values (andEric Christopher2013-04-091-13/+21
| | | | | | | | | | | therefore not at all) of the pc or statement list. We also don't need to emit the compilation dir so save so space and time and don't bother. Fix up the testcase accordingly and verify that we don't emit the attributes or the items that they use. llvm-svn: 179114
* DAGCombiner: Fold a shuffle on CONCAT_VECTORS into a new CONCAT_VECTORS if ↵Benjamin Kramer2013-04-091-0/+49
| | | | | | | | | | | | | | | | | | | | possible. This pattern occurs in SROA output due to the way vector arguments are lowered on ARM. The testcase from PR15525 now compiles into this, which is better than the code we got with the old scalarrepl: _Store: ldr.w r9, [sp] vmov d17, r3, r9 vmov d16, r1, r2 vst1.8 {d16, d17}, [r0] bx lr Differential Revision: http://llvm-reviews.chandlerc.com/D647 llvm-svn: 179106
* DW_FORM_sec_offset should be a relocation on platforms that useEric Christopher2013-04-072-5/+14
| | | | | | | | | a relocation across sections. Do this for DW_AT_stmt list in the skeleton CU and check the relocations in the debug_info section. Add a FIXME for multiple CUs. llvm-svn: 178969
* typoNadav Rotem2013-04-061-1/+1
| | | | llvm-svn: 178949
* Dwarf: use utostr on CUID to append to SmallString.Manman Ren2013-04-061-1/+1
| | | | | | | | | We used to do "SmallString += CUID", which is incorrect, since CUID will be truncated to a char. rdar://problem/13573833 llvm-svn: 178941
* Reapply r178845 with fix - Fix bug in PEI's virtual-register scavengingHal Finkel2013-04-052-24/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes PEI as previously described, but correctly handles the case where the instruction defining the virtual register to be scavenged is the first in the block. Arnold provided me with a bugpoint-reduced test case, but even that seems too large to use as a regression test. If I'm successful in cleaning it up then I'll commit that as well. Original commit message: This change fixes a bug that I introduced in r178058. After a register is scavenged using one of the available spills slots the instruction defining the virtual register needs to be moved to after the spill code. The scavenger has already processed the defining instruction so that registers killed by that instruction are available for definition in that same instruction. Unfortunately, after this, the scavenger needs to iterate through the spill code and then visit, again, the instruction that defines the now-scavenged register. In order to avoid confusion, the register scavenger needs the ability to 'back up' through the spill code so that it can again process the instructions in the appropriate order. Prior to this fix, once the scavenger reached the just-moved instruction, it would assert if it killed any registers because, having already processed the instruction, it believed they were undefined. Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar for diagnosing the problem and testing this fix. llvm-svn: 178919
* Use the target options specified on a function to reset the back-end.Bill Wendling2013-04-052-39/+70
| | | | | | | | During LTO, the target options on functions within the same Module may change. This would necessitate resetting some of the back-end. Do this for X86, because it's a Friday afternoon. llvm-svn: 178917
* Revert r178845 - Fix bug in PEI's virtual-register scavengingHal Finkel2013-04-052-67/+24
| | | | | | | | | | | | | | | | | | | | | | Reverting because this breaks one of the LTO builders. Original commit message: This change fixes a bug that I introduced in r178058. After a register is scavenged using one of the available spills slots the instruction defining the virtual register needs to be moved to after the spill code. The scavenger has already processed the defining instruction so that registers killed by that instruction are available for definition in that same instruction. Unfortunately, after this, the scavenger needs to iterate through the spill code and then visit, again, the instruction that defines the now-scavenged register. In order to avoid confusion, the register scavenger needs the ability to 'back up' through the spill code so that it can again process the instructions in the appropriate order. Prior to this fix, once the scavenger reached the just-moved instruction, it would assert if it killed any registers because, having already processed the instruction, it believed they were undefined. Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar for diagnosing the problem and testing this fix. llvm-svn: 178916
* Fix bug in PEI's virtual-register scavengingHal Finkel2013-04-052-24/+67
| | | | | | | | | | | | | | | | | | | | This change fixes a bug that I introduced in r178058. After a register is scavenged using one of the available spills slots the instruction defining the virtual register needs to be moved to after the spill code. The scavenger has already processed the defining instruction so that registers killed by that instruction are available for definition in that same instruction. Unfortunately, after this, the scavenger needs to iterate through the spill code and then visit, again, the instruction that defines the now-scavenged register. In order to avoid confusion, the register scavenger needs the ability to 'back up' through the spill code so that it can again process the instructions in the appropriate order. Prior to this fix, once the scavenger reached the just-moved instruction, it would assert if it killed any registers because, having already processed the instruction, it believed they were undefined. Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar for diagnosing the problem and testing this fix. llvm-svn: 178845
* RegisterPressure heuristics currently require signed comparisons.Andrew Trick2013-04-051-2/+2
| | | | llvm-svn: 178823
* Disable DFSResult for ConvergingScheduler.Andrew Trick2013-04-051-2/+0
| | | | | | | | For now, just save the compile time since the ConvergingScheduler heuristics don't use this analysis. We'll probably enable it later after compile-time investigation. llvm-svn: 178822
* MachineScheduler: format DEBUG output.Andrew Trick2013-04-051-22/+17
| | | | | | | I'm getting more serious about tuning and enabling on x86/ARM. Start by making the trace readable. llvm-svn: 178821
* CostModel: Add parameter to instruction cost to further classify operand valuesArnold Schwaighofer2013-04-041-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On certain architectures we can support efficient vectorized version of instructions if the operand value is uniform (splat) or a constant scalar. An example of this is a vector shift on x86. We can efficiently support for (i = 0 ; i < ; i += 4) w[0:3] = v[0:3] << <2, 2, 2, 2> but not for (i = 0; i < ; i += 4) w[0:3] = v[0:3] << x[0:3] This patch adds a parameter to getArithmeticInstrCost to further qualify operand values as uniform or uniform constant. Targets can then choose to return a different cost for instructions with such operand values. A follow-up commit will test this feature on x86. radar://13576547 llvm-svn: 178807
* Debug Info: revert 178722 for now.Manman Ren2013-04-043-15/+4
| | | | | | | | | | | | | There is a difference for FORM_ref_addr between DWARF 2 and DWARF 3+. Since Eric is against guarding DWARF 2 ref_addr with DarwinGDBCompat, we are still in discussion on how to handle this. The correct solution is to update our header to say version 4 instead of version 2 and update tool chains as well. rdar://problem/13559431 llvm-svn: 178806
* typoAdrian Prantl2013-04-041-1/+1
| | | | llvm-svn: 178804
* FormattingEli Bendersky2013-04-041-2/+2
| | | | llvm-svn: 178771
* Debug Info: according to DWARF 2, FORM_ref_addr the same size as an address onManman Ren2013-04-043-4/+15
| | | | | | | | | | | the target system. It was hard-coded to 4 bytes before. I can't get llvm to generate a ref_addr on a reasonably sized testing case. rdar://problem/13559431 llvm-svn: 178722
* Fix PR15632: No support for ppcf128 floating-point remainder on PowerPC.Bill Schmidt2013-04-032-0/+12
| | | | | | | | For this we need to use a libcall. Previously LLVM didn't implement libcall support for frem, so I've added it in the usual straightforward manner. A test case from the bug report is included. llvm-svn: 178639
* Fix grammar.Eric Christopher2013-04-031-1/+1
| | | | llvm-svn: 178624
* Remove ZeroOrMore from the option description. We don't need it here.Eric Christopher2013-04-031-1/+1
| | | | llvm-svn: 178623
* Allow MachineTraceMetrics to be used when the model has no resources.Jakob Stoklund Olesen2013-04-022-7/+11
| | | | | | | It it still possible to extract information from itineraries, for example. llvm-svn: 178582
* Don't attempt MTM heuristics without a scheduling model present.Jakob Stoklund Olesen2013-04-021-0/+4
| | | | | | This should fix the PPC buildbots. llvm-svn: 178558
* Count processor resources individually in MachineTraceMetrics.Jakob Stoklund Olesen2013-04-021-9/+144
| | | | | | | | | | | | | | | The new instruction scheduling models provide information about the number of cycles consumed on each processor resource. This makes it possible to estimate ILP more accurately than simply counting instructions / issue width. The functions getResourceDepth() and getResourceLength() now identify the limiting processor resource, and return a cycle count based on that. This gives more precise resource information, particularly in traces that use one resource a lot more than others. llvm-svn: 178553
* DAGCombiner: Merge store/loads when we have extload/truncstoresArnold Schwaighofer2013-04-021-0/+19
| | | | | | | | | | | | | | | | This is helps on architectures where i8,i16 are not legal but we have byte, and short loads/stores. Allowing us to merge copies like the one below on ARM. copy(char *a, char *b, int n) { do { int t0 = a[0]; int t1 = a[1]; b[0] = t0; b[1] = t1; radar://13536387 llvm-svn: 178546
* Merge load/store sequences with adresses: base + index + offsetArnold Schwaighofer2013-04-011-25/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We would also like to merge sequences that involve a variable index like in the example below. int index = *idx++ int i0 = c[index+0]; int i1 = c[index+1]; b[0] = i0; b[1] = i1; By extending the parsing of the base pointer to handle dags that contain a base, index, and offset we can handle examples like the one above. The dag for the code above will look something like: (load (i64 add (i64 copyfromreg %c) (i64 signextend (i8 load %index)))) (load (i64 add (i64 copyfromreg %c) (i64 signextend (i32 add (i32 signextend (i8 load %index)) (i32 1))))) The code that parses the tree ignores the intermediate sign extensions. However, if there is a sign extension it needs to be on all indexes. (load (i64 add (i64 copyfromreg %c) (i64 signextend (add (i8 load %index) (i8 1)))) vs (load (i64 add (i64 copyfromreg %c) (i64 signextend (i32 add (i32 signextend (i8 load %index)) (i32 1))))) radar://13536387 llvm-svn: 178483
* DAGCombine: visitXOR can replace a node without returning it, bail out in ↵Benjamin Kramer2013-03-301-3/+3
| | | | | | | | that case. Fixes the crash reported in PR15608. llvm-svn: 178429
* Use SmallVectorImpl instead of SmallVector at the uses.Eric Christopher2013-03-293-18/+18
| | | | llvm-svn: 178386
* Use 12 as the magic number for our abbreviation data and ourEric Christopher2013-03-293-11/+11
| | | | | | | die values. A lot of DIEs have 10 attributes in C++ code (example clang), none had more than 12. Seems like a good default. llvm-svn: 178366
* Move the construction of the skeleton compile unit after theEric Christopher2013-03-291-7/+8
| | | | | | entire original compile unit has been constructed. llvm-svn: 178365
* Remove the old CodePlacementOpt pass.Benjamin Kramer2013-03-295-444/+3
| | | | | | It was superseded by MachineBlockPlacement and disabled by default since LLVM 3.1. llvm-svn: 178349
* Fix a typoNadav Rotem2013-03-291-1/+1
| | | | llvm-svn: 178346
* [fast-isel] Add a preemptive fix for the case where we fail to materialize anChad Rosier2013-03-281-0/+2
| | | | | | | | | | | immediate in a register. I don't believe this should ever fail, but I see no harm in trying to make this code bullet proof. I've added an assert to ensure my assumtion is correct. If the assertion fires something is wrong and we should fix it, rather then just silently fall back to SelectionDAG isel. llvm-svn: 178305
* Fix target-customized spilling in the register scavengerHal Finkel2013-03-271-1/+1
| | | | | | | | | | | | This is a follow-up to r178073 (which should actually make target-customized spilling work again). I still don't have a regression test for this (but it would be good to have one; Thumb 1 and Mips16 use this callback as well). Patch by Richard Sandiford. llvm-svn: 178137
* Fix the register scavenger for targets that provide custom spillingHal Finkel2013-03-261-2/+5
| | | | | | | | | | | As pointed out by Richard Sandiford, my recent updates to the register scavenger broke targets that use custom spilling (because the new code assumed that if there were no valid spill slots, than spilling would be impossible). I don't have a test case, but it should be possible to create one for Thumb 1, Mips 16, etc. llvm-svn: 178073
* Update PEI's virtual-register-based scavenging to support multiple ↵Hal Finkel2013-03-262-22/+35
| | | | | | | | | | | | | | | | | | | simultaneous mappings The previous algorithm could not deal properly with scavenging multiple virtual registers because it kept only one live virtual -> physical mapping (and iterated through operands in order). Now we don't maintain a current mapping, but rather use replaceRegWith to completely remove the virtual register as soon as the mapping is established. In order to allow the register scavenger to return a physical register killed by an instruction for definition by that same instruction, we now call RS->forward(I) prior to eliminating virtual registers defined in I. This requires a minor update to forward to ignore virtual registers. These new features will be tested in forthcoming commits. llvm-svn: 178058
* Enhance folding of (extract_subvec (insert_subvec V1, V2, IIdx), EIdx)Michael Liao2013-03-251-21/+29
| | | | | | | | - Handle the case where the result of 'insert_subvect' is bitcasted before 'extract_subvec'. This removes the redundant insertf128/extractf128 pair on unaligned 256-bit vector load/store on vectors of non 64-bit integer. llvm-svn: 177945
* Disable some unsafe-fp-math DAG-combine transformation after legalization.Shuxin Yang2013-03-251-5/+17
| | | | | | | | | | | | | | For instance, following transformation will be disabled: x + x + x => 3.0f * x; The problem of these transformations is that it introduces a FP constant, which following Instruction-Selection pass cannot handle. Reviewed by Nadav, thanks a lot! rdar://13445387 llvm-svn: 177933
* Couple more sets of tidying.Eric Christopher2013-03-251-5/+5
| | | | llvm-svn: 177920
* Formatting.Eric Christopher2013-03-251-4/+4
| | | | llvm-svn: 177898
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