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* MachineScheduler: Move code to initialize a Candidate out of tryCandidate(); NFCMatthias Braun2016-04-221-33/+33
| | | | llvm-svn: 267191
* MachineScheduler: Limit the size of the ready list.Matthias Braun2016-04-221-1/+10
| | | | | | | | | Avoid quadratic complexity in unusually large basic blocks by limiting the size of the ready lists. Differential Revision: http://reviews.llvm.org/D19349 llvm-svn: 267189
* PostRAHazardRecocgnizer: Fix unused-private-field warningTom Stellard2016-04-221-1/+0
| | | | llvm-svn: 267160
* CodeGen: Add a stand-alone hazard recognizer passTom Stellard2016-04-223-0/+103
| | | | | | | | | | | | | | | | Summary: This new pass allows targets to use the hazard recognizer without having to also run one of the schedulers. This is useful when compiling with optimizations disabled for targets that still need noop hazards to be handled correctly. Reviewers: hfinkel, atrick Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18594 llvm-svn: 267156
* Fix -Wunused-variable in non-asserts build.Eric Liu2016-04-221-0/+1
| | | | llvm-svn: 267128
* Revert r267098 - [MachineCombiner] Support for floating-point FMA on ARM64Daniel Sanders2016-04-223-27/+4
| | | | | | It introduced buildbot failures on clang-cmake-mips, clang-ppc64le-linux, among others. llvm-svn: 267127
* Revert "Initial implementation of optimization bisect support."Vedant Kumar2016-04-2215-18/+15
| | | | | | | | This reverts commit r267022, due to an ASan failure: http://lab.llvm.org:8080/green/job/clang-stage2-cmake-RgSan_check/1549 llvm-svn: 267115
* AMDGPU/SI: add llvm.amdgcn.ps.live intrinsicNicolai Haehnle2016-04-221-0/+11
| | | | | | | | | | | | | | | | | | | | | | | Summary: This intrinsic returns true if the current thread belongs to a live pixel and false if it belongs to a pixel that we are executing only for derivative computation. It will be used by Mesa to implement gl_HelperInvocation. Note that for pixels that are killed during the shader, this implementation also returns true, but it doesn't matter because those pixels are always disabled in the EXEC mask. This unearthed a corner case in the instruction verifier, which complained about a v_cndmask 0, 1, exec, exec<imp-use> instruction. That's stupid but correct code, so make the verifier accept it as such. Reviewers: arsenm, tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19191 llvm-svn: 267102
* [MachineCombiner] Support for floating-point FMA on ARM64Gerolf Hoflehner2016-04-223-4/+27
| | | | | | | | | | | | | | | | Evaluates fmul+fadd -> fmadd combines and similar code sequences in the machine combiner. It adds support for float and double similar to the existing integer implementation. The key features are: - DAGCombiner checks whether it should combine greedily or let the machine combiner do the evaluation. This is only supported on ARM64. - It gives preference to throughput over latency: the heuristic used is to combine always in loops. The targets decides whether the machine combiner should optimize for throughput or latency. - Supports for fmadd, f(n)msub, fmla, fmls patterns - On by default at O3 ffast-math llvm-svn: 267098
* Fix more -Wunused-variable in non-asserts build.David Blaikie2016-04-211-3/+2
| | | | llvm-svn: 267077
* Fix some -Wunused-variable warnings in non-asserts builds.David Blaikie2016-04-211-5/+6
| | | | llvm-svn: 267073
* Improve error message reporting for MachineFunctionPropertiesDerek Schuff2016-04-212-2/+4
| | | | | | | | When printing the properties required by a pass, only print the properties that are set, and not those that are clear (only properties that are set are verified, clear properties are "don't-care"). llvm-svn: 267070
* [MachineBasicBlock] Make the pass argument truly mandatory whenQuentin Colombet2016-04-214-10/+10
| | | | | | | | | | | | | | splitting edges. MachineBasicBlock::SplitCriticalEdges will crash if a nullptr would have been passed for the Pass argument. Do not allow that by turning this argument into a reference. The alternative would have been to make the Pass a truly optional argument, but although this is easy to do, I was afraid users using it like this would not be aware the livness information, dominator tree and such would silently be broken. llvm-svn: 267052
* [MachineBasicBlock] Refactor SplitCriticalEdge to expose a query API.Quentin Colombet2016-04-211-27/+39
| | | | | | | | | Introduce canSplitCriticalEdge, so that clients can now query whether or not a critical edge can be split without actually needing to split it. This may be useful when gathering information for cost models for instance. llvm-svn: 267046
* [RegisterBankInfo] Change the API for the verify methods.Quentin Colombet2016-04-213-10/+15
| | | | | | | Return bool instead of void so that it is natural to put the calls into asserts. llvm-svn: 267033
* LegalizeDAG: Move unaligned load/store expansion to TLIMatt Arsenault2016-04-212-310/+304
| | | | | | | | When custom lowered, this is not called if the store is custom lowered. Move it to be a utility function so targets can easily expand unaligned accesses when custom lowering. llvm-svn: 267029
* [RegisterBankInfo] Change the representation of the partial mappings.Quentin Colombet2016-04-212-33/+26
| | | | | | | | | Instead of holding a mask, hold two value: the start index and the length of the mapping. This is a more compact representation, although less powerful. That being said, arbitrary masks would not have worked for the generic so do not allow them in the first place. llvm-svn: 267025
* DAGCombiner: Reduce 64-bit BFE pattern to pattern on 32-bit componentMatt Arsenault2016-04-211-0/+44
| | | | | | | If the extracted bits are restricted to the upper half or lower half, this can be truncated. llvm-svn: 267024
* Initial implementation of optimization bisect support.Andrew Kaylor2016-04-2115-15/+18
| | | | | | | | | | | | This patch implements a optimization bisect feature, which will allow optimizations to be selectively disabled at compile time in order to track down test failures that are caused by incorrect optimizations. The bisection is enabled using a new command line option (-opt-bisect-limit). Individual passes that may be skipped call the OptBisect object (via an LLVMContext) to see if they should be skipped based on the bisect limit. A finer level of control (disabling individual transformations) can be managed through an addition OptBisect method, but this is not yet used. The skip checking in this implementation is based on (and replaces) the skipOptnoneFunction check. Where that check was being called, a new call has been inserted in its place which checks the bisect limit and the optnone attribute. A new function call has been added for module and SCC passes that behaves in a similar way. Differential Revision: http://reviews.llvm.org/D19172 llvm-svn: 267022
* Fixed Dwarf debug info emission to skip DILexicalBlockFile entries.Amjad Aboud2016-04-212-8/+14
| | | | | | | | Before this fix, DILexicalBlockFile entries were skipped only in some cases and were not in other cases. Differential Revision: http://reviews.llvm.org/D18724 llvm-svn: 267004
* [SelectionDAG] Teach LegalizeVectorOps to directly Expand ↵Craig Topper2016-04-211-3/+5
| | | | | | | | CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF to CTTZ/CTLZ directly if those ops are Legal/Custom instead of deferring it to LegalizeOps. This is needed to support CTTZ/CTLZ Custom correctly since LegalizeOps would be too late to do the custom lowering. llvm-svn: 266951
* MachineSched: Cleanup; NFCMatthias Braun2016-04-211-32/+16
| | | | llvm-svn: 266946
* ScoreboardHazardRecognizer: unbreak TSAN by moving a static mutated variable ↵Mehdi Amini2016-04-201-15/+6
| | | | | | | to a member From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266837
* [PPC, SSP] Support PowerPC Linux stack protection.Tim Shen2016-04-192-14/+12
| | | | llvm-svn: 266809
* [SSP, 2/2] Create llvm.stackguard() intrinsic and lower it to LOAD_STACK_GUARDTim Shen2016-04-194-78/+94
| | | | | | | | | | | | | | | | | | | | | | | With this change, ideally IR pass can always generate llvm.stackguard call to get the stack guard; but for now there are still IR form stack guard customizations around (see getIRStackGuard()). Future SSP customization should go through LOAD_STACK_GUARD. There is a behavior change: stack guard values are not CSEed anymore, since we should never reuse the value in case that it has been spilled (and corrupted). See ssp-guard-spill.ll. This also cause the change of stack size and codegen in X86 and AArch64 test cases. Ideally we'd like to know if the guard created in llvm.stackprotector() gets spilled or not. If the value is spilled, discard the value and reload stack guard; otherwise reuse the value. This can be done by teaching register allocator to know how to rematerialize LOAD_STACK_GUARD and force a rematerialization (which seems hard), or check for spilling in expandPostRAPseudo. It only makes sense when the stack guard is a global variable, which requires more instructions to load. Anyway, this seems to go out of the scope of the current patch. llvm-svn: 266806
* Add a description for the PatchableFunction pass; NFCSanjoy Das2016-04-191-1/+2
| | | | llvm-svn: 266721
* Introduce a "patchable-function" function attributeSanjoy Das2016-04-194-0/+74
| | | | | | | | | | | | | | | | | Summary: The `"patchable-function"` attribute can be used by an LLVM client to influence LLVM's code generation in ways that makes the generated code easily patchable at runtime (for instance, to redirect control). Right now only one patchability scheme is supported, `"prologue-short-redirect"`, but this can be expanded in the future. Reviewers: joker.eph, rnk, echristo, dberris Subscribers: joker.eph, echristo, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D19046 llvm-svn: 266715
* [DWARF] Force a linkage_name on an inlined subprogram's abstract origin.Paul Robinson2016-04-184-18/+30
| | | | | | | | | | | | | When we suppress linkage names, for a non-inlined subprogram the name can still be found in the object-file symbol table, because we have the code address of the subprogram. This is not necessarily the case for an inlined subprogram, so we still want to emit the linkage name in the DWARF. Put this on the abstract-origin DIE because it's common to all inlined instances. Differential Revision: http://reviews.llvm.org/D18706 llvm-svn: 266692
* NFC: unify clang / LLVM atomic orderingJF Bastien2016-04-181-38/+8
| | | | | | | | | | | This makes the C11 / C++11 *ABI* atomic ordering accessible from LLVM, as discussed in http://reviews.llvm.org/D18200#inline-151433 This re-applies r266573 which I had reverted in r266576. Original review: http://reviews.llvm.org/D18875 llvm-svn: 266640
* [NFC] Header cleanupMehdi Amini2016-04-1836-56/+13
| | | | | | | | | | | | | | Removed some unused headers, replaced some headers with forward class declarations. Found using simple scripts like this one: clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap' Patch by Eugene Kosov <claprix@yandex.ru> Differential Revision: http://reviews.llvm.org/D19219 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266595
* Revert "NFC: unify clang / LLVM atomic ordering"JF Bastien2016-04-171-7/+38
| | | | | | | | | | | | | | | | This reverts commit 537951f2f16d6a8542571c7722fcbae07d4e62c2. Causes an assert in: test/Transforms/AtomicExpand/SPARC/libcalls.ll (Ordering2 != AtomicOrdering::NotAtomic && "expect atomic MO") Bot: http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-incremental_check/21724/testReport/junit/LLVM/Transforms_AtomicExpand_SPARC/libcalls_ll/ I'm not getting this assert on my local debug build, but I'll revert just to be sure. llvm-svn: 266576
* NFC: unify clang / LLVM atomic orderingJF Bastien2016-04-171-38/+7
| | | | | | | | | | | | Summary: This makes the C11 / C++11 *ABI* atomic ordering accessible from LLVM, as discussed in http://reviews.llvm.org/D18200#inline-151433 Reviewers: jyknight, reames Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D18875 llvm-svn: 266573
* [ParallelCG] SmallVector<char> -> SmallString.Davide Italiano2016-04-171-2/+2
| | | | llvm-svn: 266568
* Keep only the splitCodegen version that takes a factory.Rafael Espindola2016-04-171-19/+0
| | | | | | | This makes it much easier to see that all created TargetMachines are equivalent. llvm-svn: 266564
* Remove some unneeded headers and replace some headers with forward class ↵Mehdi Amini2016-04-162-4/+2
| | | | | | | | | | | declarations (NFC) Differential Revision: http://reviews.llvm.org/D19154 Patch by Eugene Kosov <claprix@yandex.ru> From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266524
* Do not modify a cl::opt programmatically, global mutable state is evil.Mehdi Amini2016-04-161-9/+13
| | | | | | | Found by TSAN on ThinLTO. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266514
* Update and fix LLVM_ENABLE_MODULES:Richard Smith2016-04-161-1/+0
| | | | | | | | | | | | | | | | 1) We need to add this flag prior to adding any other, in case the user has specified a -fmodule-cache-path= flag in their custom CXXFLAGS. Such a flag causes -Werror builds to fail, and thus all config checks fail, until we add the corresponding -fmodules flag. The modules selfhost bot does this, for instance. 2) Delete module maps that were putting .cpp files into modules. 3) Enable -fmodules-local-submodule-visibility, to get proper module visibility rules applied across submodules of the same module. Disable -fmodules for C builds, since that flag is not available there. llvm-svn: 266502
* Don't skip splitSeparateComponents in eliminateDeadDefs for ↵Wei Mi2016-04-152-17/+23
| | | | | | | | | | | | | | | | | | HoistSpillHelper::hoistAllSpills. Because HoistSpillHelper::hoistAllSpills is called in postOptimization, before the patch we didn't want LiveRangeEdit::eliminateDeadDefs to call splitSeparateComponents and generate unassigned new vregs. However, skipping splitSeparateComponents will make verify-machineinstrs unhappy, so I remove the early return, and use HoistSpillHelper::LRE_DidCloneVirtReg to assign physreg/stackslot for those new vregs. In addition, some code reorganization to make class HoistSpillHelper privately inheriting from LiveRangeEdit::Delegate possible. This is to be consistent with class RAGreedy and class RegisterCoalescer. Differential Revision: http://reviews.llvm.org/D19142 llvm-svn: 266489
* Switch lowering: don't add incoming PHI values from skipped bit test MBB's ↵Hans Wennborg2016-04-151-12/+26
| | | | | | | | | | | (PR27135) After r245976, LLVM will skip the last bit test case if knows it will always be true. However, we would still erroneously update PHI nodes with incoming values from the MBB that would perform the final bit test, causing -verify-machineinstrs to fail. llvm-svn: 266479
* SelectionDAGISel: rangeify a loopHans Wennborg2016-04-151-23/+20
| | | | llvm-svn: 266478
* [ParallelCG] Add a new splitCodeGen() API which takes a TargetMachineFactory.Davide Italiano2016-04-151-21/+27
| | | | | | | | This is a recommit of r266390 with a fix that will allow tests to pass (hopefully). Before we got a StringRef to M->getTargetTriple() and right after we moved the Module so we were referencing a dangling object. llvm-svn: 266456
* [PR27284] Reverse the ownership between DICompileUnit and DISubprogram.Adrian Prantl2016-04-152-28/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently each Function points to a DISubprogram and DISubprogram has a scope field. For member functions the scope is a DICompositeType. DIScopes point to the DICompileUnit to facilitate type uniquing. Distinct DISubprograms (with isDefinition: true) are not part of the type hierarchy and cannot be uniqued. This change removes the subprograms list from DICompileUnit and instead adds a pointer to the owning compile unit to distinct DISubprograms. This would make it easy for ThinLTO to strip unneeded DISubprograms and their transitively referenced debug info. Motivation ---------- Materializing DISubprograms is currently the most expensive operation when doing a ThinLTO build of clang. We want the DISubprogram to be stored in a separate Bitcode block (or the same block as the function body) so we can avoid having to expensively deserialize all DISubprograms together with the global metadata. If a function has been inlined into another subprogram we need to store a reference the block containing the inlined subprogram. Attached to https://llvm.org/bugs/show_bug.cgi?id=27284 is a python script that updates LLVM IR testcases to the new format. http://reviews.llvm.org/D19034 <rdar://problem/25256815> llvm-svn: 266446
* [MachineScheduler]Add support for store clusteringJun Bum Lim2016-04-151-35/+60
| | | | | | | | | | | | Perform store clustering just like load clustering. This change add StoreClusterMutation in machine-scheduler. To control StoreClusterMutation, added enableClusterStores() in TargetInstrInfo.h. This is enabled only on AArch64 for now. This change also add support for unscaled stores which were not handled in getMemOpBaseRegImmOfs(). llvm-svn: 266437
* Revert "[LTO] Add a new splitCodeGen() API which takes a TargetMachineFactory."Davide Italiano2016-04-151-26/+20
| | | | | | This reverts commits r266390 and r266396 as they broke some bots. llvm-svn: 266408
* [ifcnv] Don't duplicate blocks that contain convergent instructions.Justin Lebar2016-04-151-1/+31
| | | | | | | | | | | It's unsafe to duplicate blocks that contain convergent instructions during ifcnv. See the patch for details. Reviewers: hfinkel Differential Revision: http://reviews.llvm.org/D17518 llvm-svn: 266404
* [LTO] Add a new splitCodeGen() API which takes a TargetMachineFactory.Davide Italiano2016-04-151-20/+26
| | | | | | | | | This will be used in lld to avoid creating TargetMachine in two different places. See D18999 for a more detailed discussion. Differential Revision: http://reviews.llvm.org/D19139 llvm-svn: 266390
* [ScheduleDAGInstrs] Re-factor for based on review feedback. NFC.Geoff Berry2016-04-141-52/+45
| | | | | | | | | | | | | | Summary: Re-factor some code to improve clarity and style based on review comments from http://reviews.llvm.org/D18093. Reviewers: MatzeB, mcrosier Subscribers: MatzeB, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D19128 llvm-svn: 266372
* Sink DI metadata usage out of MachineInstr.h and MachineInstrBuilder.hReid Kleckner2016-04-148-0/+56
| | | | | | | | | | | MachineInstr.h and MachineInstrBuilder.h are very popular headers, widely included across all LLVM backends. It turns out that there only a handful of TUs that actually care about DI operands on MachineInstrs. After this change, touching DebugInfoMetadata.h and rebuilding llc only needs 112 actions instead of 542. llvm-svn: 266351
* [GlobalISel] Coding style and whitespace fixesTom Stellard2016-04-141-2/+2
| | | | | | | | | | Reviewers: qcolombet Subscribers: joker.eph, llvm-commits, vkalintiris Differential Revision: http://reviews.llvm.org/D19119 llvm-svn: 266342
* [CodeGen] Teach LLVM how to lower @llvm.{min,max}num to {MIN,MAX}NANDavid Majnemer2016-04-141-6/+16
| | | | | | | | | | | | | | | The behavior of {MIN,MAX}NAN differs from that of {MIN,MAX}NUM when only one of the inputs is NaN: -NUM will return the non-NaN argument while -NAN would return NaN. It is desirable to lower to @llvm.{min,max}num to -NAN if they don't have a native instruction for -NUM. Notably, ARMv7 NEON's vmin has the -NAN semantics. N.B. Of course, it is only safe to do this if the intrinsic call is marked nnan. llvm-svn: 266279
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