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* [DAGCombiner] add (sext i1 X), 1 --> zext (not i1 X)Sanjay Patel2017-04-261-6/+23
| | | | | | | | | | | | Besides better codegen, the motivation is to be able to canonicalize this pattern in IR (currently we don't) knowing that the backend is prepared for that. This may also allow removing code for special constant cases in DAGCombiner::foldSelectOfConstants() that was added in D30180. Differential Revision: https://reviews.llvm.org/D31944 llvm-svn: 301457
* [ValueTracking] Introduce a KnownBits struct to wrap the two APInts for ↵Craig Topper2017-04-261-3/+4
| | | | | | | | | | | | | | | | computeKnownBits This patch introduces a new KnownBits struct that wraps the two APInt used by computeKnownBits. This allows us to treat them as more of a unit. Initially I've just altered the signatures of computeKnownBits and InstCombine's simplifyDemandedBits to pass a KnownBits reference instead of two separate APInt references. I'll do similar to the SelectionDAG version of computeKnownBits/simplifyDemandedBits as a separate patch. I've added a constructor that allows initializing both APInts to the same bit width with a starting value of 0. This reduces the repeated pattern of initializing both APInts. Once place default constructed the APInts so I added a default constructor for those cases. Going forward I would like to add more methods that will work on the pairs. For example trunc, zext, and sext occur on both APInts together in several places. We should probably add a clear method that can be used to clear both pieces. Maybe a method to check for conflicting information. A method to return (Zero|One) so we don't write it out everywhere. Maybe a method for (Zero|One).isAllOnesValue() to determine if all bits are known. I'm sure there are many other methods we can come up with. Differential Revision: https://reviews.llvm.org/D32376 llvm-svn: 301432
* Reverts commit r301424, r301425 and r301426Sanjoy Das2017-04-261-5/+5
| | | | | | | | | | | | Commits were: "Use WeakVH instead of WeakTrackingVH in AliasSetTracker's UnkownInsts" "Add a new WeakVH value handle; NFC" "Rename WeakVH to WeakTrackingVH; NFC" The changes assumed pointers are 8 byte aligned on all architectures. llvm-svn: 301429
* Rename WeakVH to WeakTrackingVH; NFCSanjoy Das2017-04-261-5/+5
| | | | | | | | | | | | | | | | Summary: I plan to use WeakVH to mean "nulls itself out on deletion, but does not track RAUW" in a subsequent commit. Reviewers: dblaikie, davide Reviewed By: davide Subscribers: arsenm, mehdi_amini, mcrosier, mzolotukhin, jfb, llvm-commits, nhaehnle Differential Revision: https://reviews.llvm.org/D32266 llvm-svn: 301424
* [TargetLowering] fix isConstTrueVal to account for build vector truncationSanjay Patel2017-04-261-13/+17
| | | | | | | | | | | | | | Build vectors have magical truncation powers, so we have things like this: v4i1 = BUILD_VECTOR Constant:i32<1>, Constant:i32<1>, Constant:i32<1>, Constant:i32<1> v4i16 = BUILD_VECTOR Constant:i32<1>, Constant:i32<1>, Constant:i32<1>, Constant:i32<1> If we don't truncate the splat node returned by getConstantSplatNode(), then we won't find truth when ZeroOrNegativeOneBooleanContent is the rule. Differential Revision: https://reviews.llvm.org/D32505 llvm-svn: 301408
* Fix signed multiplication with overflow fallback.Ranjeet Singh2017-04-261-2/+2
| | | | | | | | | | | | | | | | For targets that don't have ISD::MULHS or ISD::SMUL_LOHI for the type and the double width type is illegal, then the two operands are sign extended to twice their size then multiplied to check for overflow. The extended upper halves were mismatched causing an incorrect result. This fixes the mismatch. A test was added for ARM V6-M where the bug was detected. Patch by James Duley. Differential Revision: https://reviews.llvm.org/D31807 llvm-svn: 301404
* [DAG] add FIXME comments for splat detection; NFCSanjay Patel2017-04-262-0/+7
| | | | llvm-svn: 301403
* PR31007 and PR27884 will be closed: a possibility to compile constants like ↵Andrew V. Tischenko2017-04-261-0/+3
| | | | | | 0bH is now supported in MS asm. llvm-svn: 301390
* Remove tailing whitespaces.Michael Liao2017-04-261-5/+5
| | | | llvm-svn: 301383
* [DAG] fix formatting of isConstantSplat(); NFCSanjay Patel2017-04-251-27/+23
| | | | llvm-svn: 301366
* Fix an assertion when skipping stack values in DWARF2 mode.Adrian Prantl2017-04-251-1/+5
| | | | | | | | The fix consists of resetting LocationKind when addMachineRegExpression fails. rdar://problem/31803010 llvm-svn: 301351
* Print complete DIExpressions in the assembler output DEBUG_VALUE comments.Adrian Prantl2017-04-251-34/+16
| | | | | | The previous code was complex, incorrect, and couldn't print everything. llvm-svn: 301333
* [DAGCombiner] Refactor to make it easy to add support for vectors in a ↵Simon Pilgrim2017-04-251-10/+10
| | | | | | future patch. NFCI. llvm-svn: 301320
* Resubmit r301309: [DebugInfo][X86] Fix handling of DBG_VALUE's in post-RA ↵Andrew Ng2017-04-253-8/+23
| | | | | | | | | scheduler. This patch reapplies r301309 with the fix to the MIR test to fix the assertion triggered by r301309. Had trimmed a little bit too much from the MIR! llvm-svn: 301317
* [SelectionDAG] Use getBuildVector helper where possible. NFCISimon Pilgrim2017-04-254-20/+17
| | | | llvm-svn: 301314
* Revert "[DebugInfo][X86] Fix handling of DBG_VALUE's in post-RA scheduler."Andrew Ng2017-04-253-23/+8
| | | | | | This reverts commit r301309 which is causing buildbot assertion failures. llvm-svn: 301312
* Bring back the ability opt out of padding zero-byte functions by not ↵Daniel Sanders2017-04-251-2/+7
| | | | | | | | | | | | | | providing a nop instruction. Summary: No test case since I'm not aware of an in-tree target that needs this. Reviewers: hans Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32398 llvm-svn: 301311
* [DebugInfo][X86] Fix handling of DBG_VALUE's in post-RA scheduler.Andrew Ng2017-04-253-8/+23
| | | | | | | | | | | | | | | | This patch fixes a bug with the updating of DBG_VALUE's in BreakAntiDependencies. Previously, it would only attempt to update the first DBG_VALUE following the instruction whose register is being changed, potentially leaving DBG_VALUE's referring to the wrong register. Now the code will update all DBG_VALUE's that immediately follow the instruction. This issue was detected as a result of an optimized codegen difference with "-g" where an X86 byte/word fixup was not performed due to a DBG_VALUE referencing the wrong register. Differential Revision: https://reviews.llvm.org/D31755 llvm-svn: 301309
* [SelectionDAG] Pull out repeated getValueType calls. NFCI.Simon Pilgrim2017-04-252-16/+16
| | | | | | Noticed in D32391. llvm-svn: 301308
* [DAGCombiner] Add vector support for (srl (trunc (srl x, c1)), c2) combine.Simon Pilgrim2017-04-251-17/+18
| | | | llvm-svn: 301305
* [SelectionDAG] Recognise splat vector isKnownToBeAPowerOfTwo one/sign bit ↵Simon Pilgrim2017-04-251-2/+2
| | | | | | shift cases. llvm-svn: 301303
* [DAGCombiner] Use SDValue::getConstantOperandVal helper where possible. NFCI.Simon Pilgrim2017-04-251-7/+5
| | | | llvm-svn: 301300
* [DAGCombiner] Use APInt::intersects to avoid tmp variable. NFCI.Simon Pilgrim2017-04-241-1/+3
| | | | llvm-svn: 301258
* Move value type list from TargetRegisterClass to TargetRegisterInfoKrzysztof Parzyszek2017-04-245-20/+20
| | | | | | Differential Revision: https://reviews.llvm.org/D31937 llvm-svn: 301234
* Revert r301231: Accidentally committed stale filesKrzysztof Parzyszek2017-04-245-18/+18
| | | | | | I forgot to commit local changes before commit. llvm-svn: 301232
* Move value type list from TargetRegisterClass to TargetRegisterInfoKrzysztof Parzyszek2017-04-245-18/+18
| | | | | | Differential Revision: https://reviews.llvm.org/D31937 llvm-svn: 301231
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-2412-27/+33
| | | | | | | | | | | | | | | 1. RegisterClass::getSize() is split into two functions: - TargetRegisterInfo::getRegSizeInBits(const TargetRegisterClass &RC) const; - TargetRegisterInfo::getSpillSize(const TargetRegisterClass &RC) const; 2. RegisterClass::getAlignment() is replaced by: - TargetRegisterInfo::getSpillAlignment(const TargetRegisterClass &RC) const; This will allow making those values depend on subtarget features in the future. Differential Revision: https://reviews.llvm.org/D31783 llvm-svn: 301221
* Don't emit CFI instructions at the end of a functionAdrian Prantl2017-04-241-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | When functions are terminated by unreachable instructions, the last instruction might trigger a CFI instruction to be generated. However, emitting it would be be illegal since the function (and thus the FDE the CFI is in) has already ended with the previous instruction. Darwin's dwarfdump --verify --eh-frame complains about this and the specification supports this. Relevant bits from the DWARF 5 standard (6.4 Call Frame Information): "[The] address_range [field in an FDE]: The number of bytes of program instructions described by this entry." "Row creation instructions: [...] The new location value is always greater than the current one." The first quotation implies that a CFI cannot describe a target address outside of the enclosing FDE's range. rdar://problem/26244988 Differential Revision: https://reviews.llvm.org/D32246 llvm-svn: 301219
* CodeGen: Add a hook for getFenceOperandTyYaxun Liu2017-04-241-2/+2
| | | | | | | | | | | | | | Currently the operand type for ATOMIC_FENCE assumes value type of a pointer in address space 0. This is fine for most targets. However for amdgcn target, the size of pointer in address space 0 depends on triple environment. For amdgiz environment, it is 64 bit but for other environment it is 32 bit. On the other hand, amdgcn target expects 32 bit fence operands independent of the target triple environment. Therefore a hook is need in target lowering for getting the fence operand type. This patch has no effect on targets other than amdgcn. Differential Revision: https://reviews.llvm.org/D32186 llvm-svn: 301215
* Add a testcase for DIExpression(DW_OP_stack_value)Adrian Prantl2017-04-242-1/+2
| | | | | | | | and relax the assertion that prohibited its emission. This fixes the assertion failure uncovered by r301093. llvm-svn: 301209
* [DAGCombiner] Updated bswap byte offset variable names to be more ↵Simon Pilgrim2017-04-241-13/+15
| | | | | | | | descriptive. NFC As discussed on D32039, use MaskByteOffset to describe the variable and also pull out repeated getOpcode() calls. llvm-svn: 301193
* [SDAG] Teach Chain Analysis about BaseIndexOffset addressing.Nirav Dave2017-04-241-2/+13
| | | | | | | | | | | | | | | | | | While we use BaseIndexOffset in FindBetterNeighborChains to appropriately realize they're almost the same address and should be improved concurrently we do not use it in isAlias using the non-index understanding FindBaseOffset instead. Adding a BaseIndexOffset check in isAlias like should allow indexed stores to be merged. FindBaseOffset to be excised in subsequent patch. Reviewers: jyknight, aditya_nandakumar, bogner Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31987 llvm-svn: 301187
* [GlobalISel] Legalize G_(S|U)DIV libcallsDiana Picus2017-04-241-12/+30
| | | | | | | | | | Treat them the same as the other binary operations that we have so far, but on integers rather than floating point types. Extract the common code into a helper. This will be used in the ARM backend. llvm-svn: 301163
* Revert "[APInt] Fix a few places that use APInt::getRawData to operate ↵Renato Golin2017-04-236-11/+14
| | | | | | | | | | | | | | | | within the normal API." This reverts commit r301105, 4, 3 and 1, as a follow up of the previous revert, which broke even more bots. For reference: Revert "[APInt] Use operator<<= where possible. NFC" Revert "[APInt] Use operator<<= instead of shl where possible. NFC" Revert "[APInt] Use ashInPlace where possible." PR32754. llvm-svn: 301111
* [ARM] ScheduleDAGRRList::DelayForLiveRegsBottomUp must consider OptionalDefsArtyom Skrobov2017-04-231-0/+12
| | | | | | | | | | | | | | | | | Summary: D30400 has enabled tADC and tSBC instructions to be unglued, thereby allowing CPSR to remain live between Thumb1 scheduling units. Most Thumb1 instructions have an OptionalDef for CPSR; but the scheduler ignored the OptionalDefs, and could unwittingly insert a flag-setting instruction in between an ADDS and the corresponding ADC. Reviewers: javed.absar, atrick, MatzeB, t.p.northover, jmolloy, rengolin Reviewed By: javed.absar Subscribers: rogfer01, efriedma, aemerson, rengolin, llvm-commits, MatzeB Differential Revision: https://reviews.llvm.org/D31081 llvm-svn: 301106
* [APInt] Fix a few places that use APInt::getRawData to operate within the ↵Craig Topper2017-04-232-7/+4
| | | | | | | | | | normal API. getRawData exposes the internal type of the APInt class directly to its users. Ideally we wouldn't expose such an implementation detail. This patch fixes a few of the easy cases by using truncate, extract, or a rotate. llvm-svn: 301105
* [APInt] Use operator<<= where possible. NFCCraig Topper2017-04-232-3/+3
| | | | llvm-svn: 301104
* [APInt] Use operator<<= instead of shl where possible. NFCCraig Topper2017-04-232-2/+2
| | | | llvm-svn: 301103
* [APInt] Use ashInPlace where possible.Craig Topper2017-04-232-2/+2
| | | | llvm-svn: 301101
* [globalisel][tablegen] Revise API for ComplexPattern operands to improve ↵Daniel Sanders2017-04-222-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | flexibility. Summary: Some targets need to be able to do more complex rendering than just adding an operand or two to an instruction. For example, it may need to insert an instruction to extract a subreg first, or it may need to perform an operation on the operand. In SelectionDAG, targets would create SDNode's to achieve the desired effect during the complex pattern predicate. This worked because SelectionDAG had a form of garbage collection that would take care of SDNode's that were created but not used due to a later predicate rejecting a match. This doesn't translate well to GlobalISel and the churn was wasteful. The API changes in this patch enable GlobalISel to accomplish the same thing without the waste. The API is now: InstructionSelector::OptionalComplexRendererFn selectArithImmed(MachineOperand &Root) const; where Root is the root of the match. The return value can be omitted to indicate that the predicate failed to match, or a function with the signature ComplexRendererFn can be returned. For example: return OptionalComplexRendererFn( [=](MachineInstrBuilder &MIB) { MIB.addImm(Immed).addImm(ShVal); }); adds two immediate operands to the rendered instruction. Immed and ShVal are captured from the predicate function. As an added bonus, this also reduces the amount of information we need to provide to GIComplexOperandMatcher. Depends on D31418 Reviewers: aditya_nandakumar, t.p.northover, qcolombet, rovka, ab, javed.absar Reviewed By: ab Subscribers: dberris, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D31761 llvm-svn: 301079
* Avoid using relocations for ref_addr in .dwo filesDavid Blaikie2017-04-223-13/+14
| | | | | | | | | | In dwo files the fixed offset can be used - if the dwos are linked into a dwp, the dwo consumer must use the dwp tables to find out where the original range of the debug_info was and resolve the "section relative" value relative to that original range - effectively avoiding/reimplementing the relocation handling. llvm-svn: 301072
* Remove the unnecessary virtual dtor from the DIEUnit hierarchy (in favor of ↵David Blaikie2017-04-222-4/+4
| | | | | | | | | protected dtor in the base, final derived classes with public non-virtual dtors) These objects are never polymorphically owned/destroyed, so the virtual dtor was unnecessary. llvm-svn: 301068
* Move Split DWARF handling to an MC option/command line argument rather than ↵David Blaikie2017-04-211-15/+4
| | | | | | | | | | | | | | | | | | | using metadata Since Split DWARF needs to name the actual .dwo file that is generated, it can't be known at the time the llvm::Module is produced as it may be merged with other Modules before the object is generated and that object may be generated with any name. By passing the Split DWARF file name when LLVM is producing object code the .dwo file name in the object file can match correctly. The support for Split DWARF for implicit modules remains the same - using metadata to store the dwo name and dwo id so that potentially multiple skeleton CUs referring to different dwo files can be generated from one llvm::Module. llvm-svn: 301062
* Re-commit r301040 "X86: Don't emit zero-byte functions on Windows"Hans Wennborg2017-04-212-9/+12
| | | | | | | | | In addition to the original commit, tighten the condition for when to pad empty functions to COFF Windows. This avoids running into problems when targeting e.g. Win32 AMDGPU, which caused test failures when this was committed initially. llvm-svn: 301047
* Revert r301040 "X86: Don't emit zero-byte functions on Windows"Hans Wennborg2017-04-212-11/+9
| | | | | | This broke almost all bots. Reverting while fixing. llvm-svn: 301041
* X86: Don't emit zero-byte functions on WindowsHans Wennborg2017-04-212-9/+11
| | | | | | | | | | | | | | | | | | Empty functions can lead to duplicate entries in the Guard CF Function Table of a binary due to multiple functions sharing the same RVA, causing the kernel to refuse to load that binary. We had a terrific bug due to this in Chromium. It turns out we were already doing this for Mach-O in certain situations. This patch expands the code for that in AsmPrinter::EmitFunctionBody() and renames TargetInstrInfo::getNoopForMachoTarget() to simply getNoop() since it seems it was used for not just Mach-O anyway. Differential Revision: https://reviews.llvm.org/D32330 llvm-svn: 301040
* [AArch64] Improve code generation for logical instructions takingAkira Hatanaka2017-04-211-30/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | immediate operands. This commit adds an AArch64 dag-combine that optimizes code generation for logical instructions taking immediate operands. The optimization uses demanded bits to change a logical instruction's immediate operand so that the immediate can be folded into the immediate field of the instruction. This recommits r300932 and r300930, which was causing dag-combine to loop forever. The problem was that optimizeLogicalImm was returning true even when there was no change to the immediate node (which happened when the immediate was all zeros or ones), which caused dag-combine to push and pop the same node to the work list over and over again without making any progress. This commit fixes the bug by returning false early in optimizeLogicalImm if the immediate is all zeros or ones. Also, it changes the code to compare the immediate with 0 or Mask rather than calling countPopulation. rdar://problem/18231627 Differential Revision: https://reviews.llvm.org/D5591 llvm-svn: 301019
* Revert r300932 and r300930.Akira Hatanaka2017-04-211-36/+30
| | | | | | | | | It seems that r300930 was creating an infinite loop in dag-combine when compling the following file: MultiSource/Benchmarks/MiBench/consumer-typeset/z21.c llvm-svn: 300940
* [AArch64] Improve code generation for logical instructions takingAkira Hatanaka2017-04-211-30/+36
| | | | | | | | | | | | | | | | | | | | immediate operands. This commit adds an AArch64 dag-combine that optimizes code generation for logical instructions taking immediate operands. The optimization uses demanded bits to change a logical instruction's immediate operand so that the immediate can be folded into the immediate field of the instruction. This recommits r300913, which broke bots because I didn't fix a call to ShrinkDemandedConstant in SIISelLowering.cpp after changing the APIs of TargetLoweringOpt and TargetLowering. rdar://problem/18231627 Differential Revision: https://reviews.llvm.org/D5591 llvm-svn: 300930
* Revert "[AArch64] Improve code generation for logical instructions taking"Akira Hatanaka2017-04-201-36/+30
| | | | | | | | This reverts r300913. This broke bots. llvm-svn: 300916
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