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* Add CoalescerPair helper class.Jakob Stoklund Olesen2010-06-153-40/+174
| | | | | | | | | | | | | | | | | | | | Given a copy instruction, CoalescerPair can determine which registers to coalesce in order to eliminate the copy. It deals with all the subreg fun to determine a tuple (DstReg, SrcReg, SubIdx) such that: - SrcReg is a virtual register that will disappear after coalescing. - DstReg is a virtual or physical register whose live range will be extended. - SubIdx is 0 when DstReg is a physical register. - SrcReg can be joined with DstReg:SubIdx. CoalescerPair::isCoalescable() determines if another copy instruction is compatible with the same tuple. This fixes some NEON miscompilations where shuffles are getting coalesced as if they were copies. The CoalescerPair class will replace a lot of the spaghetti logic in JoinCopy later. llvm-svn: 105997
* Generalize the pre-coalescing of extract_subregs feeding reg_sequences,Bob Wilson2010-06-151-33/+83
| | | | | | | | | replacing the overly conservative checks that I had introduced recently to deal with correctness issues. This makes a pretty noticable difference in our testcases where reg_sequences are used. I've updated one test to check that we no longer emit the unnecessary subreg moves. llvm-svn: 105991
* Update CMake build.Ted Kremenek2010-06-151-2/+2
| | | | llvm-svn: 105987
* More dbg_value cleanup so the presence of debug info doesn't affect code-gen.Jim Grosbach2010-06-141-2/+21
| | | | | | | Make sure to skip the dbg_value instructions when moving dups out of the diamond. rdar://7797940 llvm-svn: 105965
* - Do away with SimpleHazardRecognizer.h. It's not used and offers little value.Evan Cheng2010-06-145-225/+20
| | | | | | - Rename ExactHazardRecognizer to PostRAHazardRecognizer and move its header to include to allow targets to extend it. llvm-svn: 105959
* Avoid uncessary array copying.Evan Cheng2010-06-141-7/+19
| | | | llvm-svn: 105955
* fix a -Wbool-conversions warning from clang.Chris Lattner2010-06-141-1/+1
| | | | llvm-svn: 105942
* When performing the Horrible Hack(tm-Duncan) on the EH code to convert aBill Wendling2010-06-121-26/+49
| | | | | | | | clean-up to a catch-all after inlining, take into account that there could be filter IDs as well. The presence of filters don't mean that the selector catches anything. It's just metadata information. llvm-svn: 105872
* Allow target to provide its own hazard recognizer to post-ra scheduler.Evan Cheng2010-06-121-6/+16
| | | | llvm-svn: 105862
* Code formatting.Evan Cheng2010-06-121-5/+3
| | | | llvm-svn: 105861
* Support for nested functions/classes in debug output. (Again.) Radar 7424645.Stuart Hastings2010-06-111-1/+23
| | | | llvm-svn: 105828
* Code refactoring, no functionality changes.Evan Cheng2010-06-102-83/+87
| | | | llvm-svn: 105775
* Mark physregs defined by inline asm as implicit.Jakob Stoklund Olesen2010-06-091-2/+6
| | | | | | | This is a bit of a hack to make inline asm look more like call instructions. It would be better to produce correct dead flags during isel. llvm-svn: 105749
* Allow target to place 2-address pass inserted copies in better spots. Thumb2 ↵Evan Cheng2010-06-091-1/+6
| | | | | | will use this to try to avoid breaking up IT blocks. llvm-svn: 105745
* It's an error to translate this:Bill Wendling2010-06-091-0/+20
| | | | | | | | | | | | | | | | | | | | %reg1025 = <sext> %reg1024 ... %reg1026 = SUBREG_TO_REG 0, %reg1024, 4 into this: %reg1025 = <sext> %reg1024 ... %reg1027 = EXTRACT_SUBREG %reg1025, 4 %reg1026 = SUBREG_TO_REG 0, %reg1027, 4 The problem here is that SUBREG_TO_REG is there to assert that an implicit zext occurs. It doesn't insert a zext instruction. If we allow the EXTRACT_SUBREG here, it will give us the value after the <sext>, not the original value of %reg1024 before <sext>. llvm-svn: 105741
* Add argument name comments.Jakob Stoklund Olesen2010-06-091-2/+6
| | | | llvm-svn: 105665
* Fix a mistake in my previous change r105437: don't access operand 2 and assumeBob Wilson2010-06-071-3/+2
| | | | | | | that it is an immediate before checking that the instruction is an EXTRACT_SUBREG. llvm-svn: 105585
* Add some basic debug output.Dan Gohman2010-06-071-0/+4
| | | | llvm-svn: 105561
* Cleanup. Process the dbg_values separatelyJim Grosbach2010-06-071-18/+16
| | | | llvm-svn: 105554
* Move exit check where it really belongs.Jim Grosbach2010-06-071-4/+4
| | | | llvm-svn: 105541
* Revert 105492 & 105493 due to a testcase regression. Radar 7424645.Stuart Hastings2010-06-051-18/+1
| | | | llvm-svn: 105511
* Fix some liveout handling related to tail calls, see comments.Dale Johannesen2010-06-051-1/+6
| | | | | | | I don't think this ever resulted in problems on x86, but it would on ARM. llvm-svn: 105509
* Re-apply 105308 with fix.Evan Cheng2010-06-041-7/+13
| | | | llvm-svn: 105502
* Make if-conversion ignore dbg_value instructions in its analysis. rdar://7797940Jim Grosbach2010-06-041-4/+23
| | | | llvm-svn: 105498
* Support for nested functions/classes in debug output. Radar 7424645.Stuart Hastings2010-06-041-1/+18
| | | | llvm-svn: 105492
* Skip dbg_value instructions when scanning instructions in register scavenging.Jim Grosbach2010-06-041-0/+4
| | | | llvm-svn: 105481
* Keep track of the call instructions whose clobber lists were skipped during fastJakob Stoklund Olesen2010-06-041-0/+17
| | | | | | | | | | | register allocation. Process all of the clobber lists at the end of the function, marking the registers as used in MachineRegisterInfo. This is necessary in case the calls clobber callee-saved registers (sic). llvm-svn: 105473
* Fixed a bug during widening where we would avoid legalizing a node. When weMon P Wang2010-06-041-31/+36
| | | | | | | | | replace an OpA with a widened OpB, it is possible to get new uses of OpA due to CSE when recursively updating nodes. Since OpA has been processed, the new uses are not examined again. The patch checks if this occurred and it it did, updates the new uses of OpA to use OpB. llvm-svn: 105453
* Add some missing checks in TwoAddressInstructionPass::CoalesceExtSubRegs.Bob Wilson2010-06-031-4/+21
| | | | | | | | | | | Check that all the instructions are in the same basic block, that the EXTRACT_SUBREGs write to the same subregs that are being extracted, and that the source and destination registers are in the same regclass. Some of these constraints can be relaxed with a bit more work. Jakob suggested that the loop that checks for subregs when NewSubIdx != 0 should use the "nodbg" iterator, so I made that change here, too. llvm-svn: 105437
* Cleanup 80-column and trim trailing whitespaceJim Grosbach2010-06-031-33/+33
| | | | llvm-svn: 105435
* Fix SimplifyDemandedBits' AssertZext logic to demand all the bits. ItDan Gohman2010-06-031-4/+8
| | | | | | needs to demand the high bits because it's asserting that they're zero. llvm-svn: 105406
* Revert 105308.Bob Wilson2010-06-031-1/+4
| | | | llvm-svn: 105399
* Machine sink could potentially sink instructions into a block where the physicalBill Wendling2010-06-031-4/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | registers it defines then interfere with an existing preg live range. For instance, if we had something like these machine instructions: BB#0 ... = imul ... EFLAGS<imp-def,dead> test ..., EFLAGS<imp-def> jcc BB#2 EFLAGS<imp-use> BB#1 ... ; fallthrough to BB#2 BB#2 ... ; No code that defines EFLAGS jcc ... EFLAGS<imp-use> Machine sink will come along, see that imul implicitly defines EFLAGS, but because it's "dead", it assumes that it can move imul into BB#2. But when it does, imul's "dead" imp-def of EFLAGS is raised from the dead (a zombie) and messes up the condition code for the jump (and pretty much anything else which relies upon it being correct). The solution is to know which pregs are live going into a basic block. However, that information isn't calculated at this point. Nor does the LiveVariables pass take into account non-allocatable physical registers. In lieu of this, we do a *very* conservative pass through the basic block to determine if a preg is live coming out of it. llvm-svn: 105387
* One underscore, not two.Eric Christopher2010-06-031-1/+1
| | | | llvm-svn: 105379
* Implement expansion in type legalization for add/sub with overflow. TheEli Friedman2010-06-032-0/+73
| | | | | | | | | | expansion is the same as that used by LegalizeDAG. The resulting code sucks in terms of performance/codesize on x86-32 for a 64-bit operation; I haven't looked into whether different expansions might be better in general. llvm-svn: 105378
* Use the fast register allocator by default for -O0 builds.Jakob Stoklund Olesen2010-06-031-1/+1
| | | | | | This affects both llvm-gcc and clang. llvm-svn: 105372
* Use readsWritesVirtualRegister instead of counting uses and defs when insertingJakob Stoklund Olesen2010-06-031-46/+8
| | | | | | | | | | | | | spills and reloads. This means that a partial define of a register causes a reload so the other parts of the register are preserved. The reload can be prevented by adding an <imp-def> operand for the full register. This is already done by the coalescer and live interval analysis where relevant. llvm-svn: 105369
* Add full register <imp-def> operands when the coalescer is creating partialJakob Stoklund Olesen2010-06-021-50/+50
| | | | | | | | | register updates. These operands tell the spiller that the other parts of the partially defined register are don't-care, and a reload is not necessary. llvm-svn: 105361
* Compulsive reformating. No functionalitical changes.Bill Wendling2010-06-021-11/+19
| | | | llvm-svn: 105359
* Slightly change the meaning of the reMaterialize target hook when the originalJakob Stoklund Olesen2010-06-026-15/+29
| | | | | | | | | | | | | | | | | | | | | | | instruction defines subregisters. Any existing subreg indices on the original instruction are preserved or composed with the new subreg index. Also substitute multiple operands mentioning the original register by using the new MachineInstr::substituteRegister() function. This is necessary because there will soon be <imp-def> operands added to non read-modify-write partial definitions. This instruction: %reg1234:foo = FLAP %reg1234<imp-def> will reMaterialize(%reg3333, bar) like this: %reg3333:bar-foo = FLAP %reg333:bar<imp-def> Finally, replace the TargetRegisterInfo pointer argument with a reference to indicate that it cannot be NULL. llvm-svn: 105358
* Remove the TargetRegisterClass member from CalleeSavedInfoRafael Espindola2010-06-021-12/+19
| | | | llvm-svn: 105344
* Skip identical instruction while calculating DBG_VALUE range.Devang Patel2010-06-021-1/+4
| | | | llvm-svn: 105340
* Rename canCombinedSubRegIndex method to something more grammatically correctBob Wilson2010-06-021-2/+2
| | | | | | and tidy up the comment describing it. llvm-svn: 105339
* Use local small vector.Devang Patel2010-06-022-4/+3
| | | | llvm-svn: 105332
* Not all entries in the range will have an SUnit. Check for that when lookingJim Grosbach2010-06-022-0/+2
| | | | | | for debug information. llvm-svn: 105324
* Remove uses of getCalleeSavedRegClasses from outside theRafael Espindola2010-06-021-7/+3
| | | | | | | backends and removes the virtual declaration. With that out of the way I should be able to cleanup one backend at a time. llvm-svn: 105321
* Enable machine cse of instructions which define physical registers.Evan Cheng2010-06-021-4/+1
| | | | llvm-svn: 105308
* Fix an obvious mistake: don't change the operands until all of them have beenBob Wilson2010-06-021-2/+0
| | | | | | checked and it is safe to proceed with the changes. llvm-svn: 105304
* Update debug information when breaking anti-dependencies. rdar://7759363Jim Grosbach2010-06-012-1/+31
| | | | llvm-svn: 105300
* Properly compose subregister indices when coalescing.Jakob Stoklund Olesen2010-06-012-14/+3
| | | | | | | The comment about ordering of subreg indices is no longer true. This exposed a bug in the new substVirtReg method that is also fixed. llvm-svn: 105294
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