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* MIR Parser: Report an error when a fixed stack object is redefined.Alex Lorenz2015-08-101-2/+6
| | | | llvm-svn: 244534
* use range-based for loop; NFCISanjay Patel2015-08-101-5/+5
| | | | llvm-svn: 244531
* MIR Serialization: Serialize the liveout register mask machine operands.Alex Lorenz2015-08-104-0/+47
| | | | llvm-svn: 244529
* fix minsize detection: minsize attribute implies optimizing for sizeSanjay Patel2015-08-101-3/+1
| | | | llvm-svn: 244528
* NFC. Fix some format issues in lib/CodeGen/MachineBasicBlock.cpp.Cong Hou2015-08-101-11/+13
| | | | llvm-svn: 244518
* MachineVerifier: Handle the optional def operand in a PATCHPOINT instruction.Alex Lorenz2015-08-101-1/+4
| | | | | | | | | | | | The PATCHPOINT instructions have a single optional defined register operand, but the machine verifier can't verify the optional defined register operands. This commit makes sure that the machine verifier won't report an error when a PATCHPOINT instruction doesn't have its optional defined register operand. This change will allow us to enable the machine verifier for the code generation tests for the patchpoint intrinsics. Reviewers: Juergen Ributzka llvm-svn: 244513
* remove function names from comments; NFCSanjay Patel2015-08-101-22/+20
| | | | llvm-svn: 244509
* StackMap: FastISel: Add an appropriate number of immediate operands to theAlex Lorenz2015-08-101-3/+6
| | | | | | | | | | | | | | | | | | frame setup instruction. This commit ensures that the stack map lowering code in FastISel adds an appropriate number of immediate operands to the frame setup instruction. The previous code added just one immediate operand, which was fine for a target like AArch64, but on X86 the ADJCALLSTACKDOWN64 instruction needs two explicit operands. This caused the machine verifier to report an error when the old code added just one. Reviewers: Juergen Ributzka Differential Revision: http://reviews.llvm.org/D11853 llvm-svn: 244508
* x86: Emit LAHF/SAHF instead of PUSHF/POPFJF Bastien2015-08-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NaCl's sandbox doesn't allow PUSHF/POPF out of security concerns (priviledged emulators have forgotten to mask system bits in the past, and EFLAGS's DF bit is a constant source of hilarity). Commit r220529 fixed PR20376 by saving cmpxchg's flags result using EFLAGS, this commit now generated LAHF/SAHF instead, for all of x86 (not just NaCl) because it leads to an overall performance gain over PUSHF/POPF. As with the previous patch this code generation is pretty bad because it occurs very later, after register allocation, and in many cases it rematerializes flags which were already available (e.g. already in a register through SETE). Fortunately it's somewhat rare that this code needs to fire. I did [[ https://github.com/jfbastien/benchmark-x86-flags | a bit of benchmarking ]], the results on an Intel Haswell E5-2690 CPU at 2.9GHz are: | Time per call (ms) | Runtime (ms) | Benchmark | | 0.000012514 | 6257 | sete.i386 | | 0.000012810 | 6405 | sete.i386-fast | | 0.000010456 | 5228 | sete.x86-64 | | 0.000010496 | 5248 | sete.x86-64-fast | | 0.000012906 | 6453 | lahf-sahf.i386 | | 0.000013236 | 6618 | lahf-sahf.i386-fast | | 0.000010580 | 5290 | lahf-sahf.x86-64 | | 0.000010304 | 5152 | lahf-sahf.x86-64-fast | | 0.000028056 | 14028 | pushf-popf.i386 | | 0.000027160 | 13580 | pushf-popf.i386-fast | | 0.000023810 | 11905 | pushf-popf.x86-64 | | 0.000026468 | 13234 | pushf-popf.x86-64-fast | Clearly `PUSHF`/`POPF` are suboptimal. It doesn't really seems to be worth teaching LLVM about individual flags, at least not for this purpose. Reviewers: rnk, jvoung, t.p.northover Subscribers: llvm-commits Differential revision: http://reviews.llvm.org/D6629 llvm-svn: 244503
* Trace copies when checking for rematerializability in spill weight calculationRobert Lougher2015-08-105-8/+43
| | | | | | | | | | | | | | | PR24139 contains an analysis of poor register allocation. One of the findings was that when calculating the spill weight, a rematerializable interval once split is no longer rematerializable. This is because the isRematerializable check in CalcSpillWeights.cpp does not follow the copies introduced by live range splitting (after splitting, the live interval register definition is a copy which is not rematerializable). Reviewers: qcolombet Differential Revision: http://reviews.llvm.org/D11686 llvm-svn: 244439
* Fix some comment typos.Benjamin Kramer2015-08-0813-36/+37
| | | | llvm-svn: 244402
* MIR Serialization: Serialize the base alignment for the machine memory operands.Alex Lorenz2015-08-074-4/+18
| | | | llvm-svn: 244357
* MIR Serialization: Serialize the offsets for the machine memory operands.Alex Lorenz2015-08-072-1/+6
| | | | llvm-svn: 244356
* MIR Parser: Extract the parsing of the operand's offset into a new method. NFC.Alex Lorenz2015-08-071-2/+10
| | | | | | | | This commit extract the code that parses the 64-bit offset from the method 'parseOperandsOffset' to a new method 'parseOffset' so that we can reuse it when parsing the offset for the machine memory operands. llvm-svn: 244355
* [MC/Dwarf] Allow to specify custom parameters for linetable emission.Frederic Riss2015-08-071-1/+2
| | | | | | | | | NFC patch for current users, but llvm-dsymutil will use the new functionality to adapt to the input linetable. Based on a patch by Adrian Prantl. llvm-svn: 244318
* Revert "Make global aliases have symbol size equal to their type"John Brawn2015-08-071-10/+0
| | | | | | | This reverts r242520, as it caused pr24379. Also removes part of the test added by r243874 that checks the size of alias symbols. llvm-svn: 244313
* ShrinkWrap.cpp: Tweak r244235 for a non-functional member, PredicateFtor. ↵NAKAMURA Takumi2015-08-071-2/+2
| | | | | | [-Wdocumentation] llvm-svn: 244309
* MIR Serialization: Fix serialization of unnamed IR block references.Alex Lorenz2015-08-062-11/+33
| | | | | | | | The block address machine operands can reference IR blocks in other functions. This commit fixes a bug where the references to unnamed IR blocks in other functions weren't serialized correctly. llvm-svn: 244299
* MIR Parser: Simplify the token's string value handling.Alex Lorenz2015-08-063-56/+67
| | | | | | | | | | | | | | | | | This commit removes the 'StringOffset' and 'HasStringValue' fields from the MIToken struct and simplifies the 'stringValue' method which now returns the new 'StringValue' field. This commit also adopts a different way of initializing the lexed tokens - instead of constructing a new MIToken instance, the lexer resets the old token using the new 'reset' method and sets its attributes using the new 'setStringValue', 'setOwnedStringValue', and 'setIntegerValue' methods. Reviewers: Sean Silva Differential Revision: http://reviews.llvm.org/D11792 llvm-svn: 244295
* Revert accidentally committed WinEHPrepare changesDavid Majnemer2015-08-061-373/+8
| | | | | | This reverts commit r244272, r244273, r244274, and r244275. llvm-svn: 244278
* PHIs don't need to be postprocessedDavid Majnemer2015-08-061-31/+6
| | | | llvm-svn: 244275
* Handle PHI nodes prefacing EH pads tooDavid Majnemer2015-08-061-13/+87
| | | | llvm-svn: 244274
* handle phi nodesDavid Majnemer2015-08-061-4/+27
| | | | llvm-svn: 244273
* [WinEHPrepare] Add rudimentary support for the new EH instructionsDavid Majnemer2015-08-061-8/+301
| | | | | | | | | | | | | | | | | | | | | | | Summary: This adds somewhat basic preparation functionality including: - Formation of funclets via coloring basic blocks. - Cloning of polychromatic blocks to ensure that funclets have unique program counters. - Demotion of values used between different funclets. - Some amount of cleanup once we have removed predecessors from basic blocks. - Verification that we are left with a CFG that makes some amount of sense. N.B. Arguments and numbering still need to be done. Reviewers: rnk, JosephTremoulet Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11750 llvm-svn: 244272
* Rename inst_range() to instructions() for consistency. NFCNico Rieck2015-08-061-1/+1
| | | | llvm-svn: 244248
* Fix possible infinite loop in shrink wrapping when searching for save/restoreKit Barton2015-08-061-6/+24
| | | | | | | | | | | | | | | | | | | | points. There is an infinite loop that can occur in Shrink Wrapping while searching for the Save/Restore points. Part of this search checks whether the save/restore points are located in different loop nests and if so, uses the (post) dominator trees to find the immediate (post) dominator blocks. However, if the current block does not have any immediate (post) dominators then this search will result in an infinite loop. This can occur in code containing an infinite loop. The modification checks whether the immediate (post) dominator is different from the current save/restore block. If it is not, then the search terminates and the current location is not considered as a valid save/restore point for shrink wrapping. Phabricator: http://reviews.llvm.org/D11607 llvm-svn: 244247
* MIR Parser: Report an error when parsing duplicate memory operand flags.Alex Lorenz2015-08-061-1/+5
| | | | llvm-svn: 244240
* Revert r244154 which causes some build failure. See ↵Cong Hou2015-08-064-61/+40
| | | | | | https://llvm.org/bugs/show_bug.cgi?id=24377. llvm-svn: 244239
* This patch changes the interface to enable the shrink wrapping optimization. Kit Barton2015-08-062-22/+50
| | | | | | | | | | | | | | | It adds a new constructor, which takes a std::function predicate function that is run at the beginning of shrink wrapping to determine whether the optimization should run on the given machine function. The std::function can be overridden by each target, allowing target-specific decisions to be made on each machine function. This is necessary for PowerPC, as the decision to run shrink wrapping is partially based on the ABI. Futhermore, this operates nicely with the GCC iFunc capability, which allows option overrides on a per-function basis. Phabricator: http://reviews.llvm.org/D11421 llvm-svn: 244235
* MIR Serialization: Serialize the 'invariant' machine memory operand flag.Alex Lorenz2015-08-064-3/+11
| | | | llvm-svn: 244230
* Fix an alignment error in `llvm::expandAtomicRMWToCmpXchg` without breaking ↵Richard Diamond2015-08-061-1/+1
| | | | | | | | | | | | | | the build where X86 isn't enabled. Summary: Divide the primitive size in bits by eight so the initial load's alignment is in bytes as expected. Tested with the included unit test. Reviewers: rengolin, jfb Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11804 llvm-svn: 244229
* MIR Serialization: Serialize the 'non-temporal' machine memory operand flag.Alex Lorenz2015-08-064-1/+10
| | | | llvm-svn: 244228
* Revert "Divide the primitive size in bits by eight so the initial load's ↵Renato Golin2015-08-061-1/+1
| | | | | | | | | alignment is in bytes as expected. Tested with the included unit test." This reverts commit r244155, as it was breaking the buildbots for too long. Should be reapplied with proper fix. llvm-svn: 244205
* [PM/AA] Hoist the interface for BasicAA into a header file.Chandler Carruth2015-08-061-0/+1
| | | | | | | | | | | | | This is the first mechanical step in preparation for making this and all the other alias analysis passes available to the new pass manager. I'm factoring out all the totally boring changes I can so I'm moving code around here with no other changes. I've even minimized the formatting churn. I'll reformat and freshen comments on the interface now that its located in the right place so that the substantive changes don't triger this. llvm-svn: 244197
* [PM/AA] Simplify the AliasAnalysis interface by removing a wrapperChandler Carruth2015-08-061-5/+7
| | | | | | | | | | | | | | | | around a DataLayout interface in favor of directly querying DataLayout. This wrapper specifically helped handle the case where this no DataLayout, but LLVM now requires it simplifynig all of this. I've updated callers to directly query DataLayout. This in turn exposed a bunch of places where we should have DataLayout readily available but don't which I've fixed. This then in turn exposed that we were passing DataLayout around in a bunch of arguments rather than making it readily available so I've also fixed that. No functionality changed. llvm-svn: 244189
* MIR Serialization: Initial serialization of the machine operand target flags.Alex Lorenz2015-08-064-13/+91
| | | | | | | | | | | | This commit implements the initial serialization of the machine operand target flags. It extends the 'TargetInstrInfo' class to add two new methods that help to provide text based serialization for the target flags. This commit can serialize only the X86 target flags, and the target flags for the other targets will be serialized in the follow-up commits. Reviewers: Duncan P. N. Exon Smith llvm-svn: 244185
* If the "CodeView" module flag is set, emit codeview instead of DWARFReid Kleckner2015-08-052-12/+5
| | | | | | | | | | | | | | Summary: Emit both DWARF and CodeView if "CodeView" and "Dwarf Version" module flags are set. Reviewers: majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11756 llvm-svn: 244158
* MIR Serialization: Serialize the machine operand's offset.Alex Lorenz2015-08-054-9/+60
| | | | | | | This commit serializes the offset for the following operands: target index, global address, external symbol, constant pool index, and block address. llvm-svn: 244157
* Divide the primitive size in bits by eight so the initial load's alignment is inRichard Diamond2015-08-051-1/+1
| | | | | | bytes as expected. Tested with the included unit test. llvm-svn: 244155
* Record whether the weights on out-edges from a MBB are normalized.Cong Hou2015-08-054-40/+61
| | | | | | | | | | | | 1. Create a utility function normalizeEdgeWeights() in MachineBranchProbabilityInfo that normalizes a list of edge weights so that the sum of then can fit in uint32_t. 2. Provide an interface in MachineBasicBlock to normalize its successors' weights. 3. Add a flag in MachineBasicBlock that tracks whether its successors' weights are normalized. 4. Provide an overload of getSumForBlock that accepts a non-const pointer to a MBB so that it can force normalizing this MBB's successors' weights. 5. Update several uses of getSumForBlock() by eliminating the once needed weight scale. Differential Revision: http://reviews.llvm.org/D11442 llvm-svn: 244154
* Revert "Fix MO's analyzePhysReg, it was confusing sub- and super-registers. ↵JF Bastien2015-08-051-1/+1
| | | | | | | | Problem pointed out by Michael Hordijk." I mistakenly committed the patch for D6629, and was trying to commit another. Reverting until it gets proper signoff. llvm-svn: 244121
* Fix MO's analyzePhysReg, it was confusing sub- and super-registers. Problem ↵JF Bastien2015-08-051-1/+1
| | | | | | pointed out by Michael Hordijk. llvm-svn: 244120
* Write access test.Richard Diamond2015-08-051-1/+2
| | | | llvm-svn: 244103
* MIR Parser: Report an error when parsing large immediate operands.Alex Lorenz2015-08-051-2/+1
| | | | llvm-svn: 244100
* MIR Serialization: Serialize the typed immediate integer machine operands.Alex Lorenz2015-08-054-0/+33
| | | | llvm-svn: 244098
* MIR Parser: Extract the IR constant parsing code into a new method. NFC.Alex Lorenz2015-08-051-7/+14
| | | | | | | | This commit extracts the code that parses the IR constant values into a new method named 'parseIRConstant' in the 'MIParser' class. The new method will be reused by the code that parses the typed integer immediate machine operands. llvm-svn: 244093
* MIR Parser: Report an error when parsing duplicate register flags.Alex Lorenz2015-08-051-1/+5
| | | | llvm-svn: 244081
* [TTI] Make the cost APIs in TargetTransformInfo consistently use 'int'Chandler Carruth2015-08-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | rather than 'unsigned' for their costs. For something like costs in particular there is a natural "negative" value, that of savings or saved cost. As a consequence, there is a lot of code that subtracts or creates negative values based on cost, all of which is prone to awkwardness or bugs when dealing with an unsigned type. Similarly, we *never* want these values to wrap, as that would cause Very Bad code generation (likely percieved as an infinite loop as we try to emit over 2^32 instructions or some such insanity). All around 'int' seems a much better fit for these basic metrics. I've added asserts to ensure that at least the TTI interface never returns negative numbers here. If we ever have a use case for negative numbers, we can remove this, but this way a bug where someone used '-1' to produce a 'very large' cost will be caught by the assert. This passes all tests, and is also UBSan clean. No functional change intended. Differential Revision: http://reviews.llvm.org/D11741 llvm-svn: 244080
* MIR Serialization: Serialize the 'early-clobber' register operand flag.Alex Lorenz2015-08-054-2/+10
| | | | llvm-svn: 244075
* MIR Serialization: Serialize the 'debug-use' register operand flag.Alex Lorenz2015-08-054-2/+11
| | | | llvm-svn: 244071
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