summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
Commit message (Collapse)AuthorAgeFilesLines
* Adds support for spilling previously allocated live intervals toAndrew Trick2010-11-084-88/+207
| | | | | | | | | handle cases in which a register is unavailable for spill code. Adds LiveIntervalUnion::extract. While processing interferences on a live virtual register, reuses the same Query object for each physcial reg. llvm-svn: 118423
* Add registry hook for assembly text outputChe-Liang Chiou2010-11-081-4/+5
| | | | llvm-svn: 118394
* Prune includes.Benjamin Kramer2010-11-063-7/+7
| | | | llvm-svn: 118342
* When passing a parameter using the 'byval' mechanism, inline code needs to ↵Duncan Sands2010-11-051-0/+2
| | | | | | | | | | | | | be used to perform the copy, which may be of lots of memory [*]. It would be good if the fall-back code generated something reasonable, i.e. did the copy in a loop, rather than vast numbers of loads and stores. Add a note about this. Currently target specific code seems to always kick in so this is more of a theoretical issue rather than a practical one now that X86 has been fixed. [*] It's amazing how often people pass mega-byte long arrays by copy... llvm-svn: 118275
* Add 118023 back, but with proper spelling for .uleb128/.sleb128.Rafael Espindola2010-11-041-7/+6
| | | | llvm-svn: 118254
* Revert previous patch. Some targets don't support uleb and sayRafael Espindola2010-11-041-6/+7
| | | | | | they do :-( llvm-svn: 118250
* MCize.Rafael Espindola2010-11-041-7/+6
| | | | llvm-svn: 118249
* In the calling convention logic, ValVT is always a legal type,Duncan Sands2010-11-041-1/+1
| | | | | | | and as such can be represented by an MVT - the more complicated EVT is not needed. Use MVT for ValVT everywhere. llvm-svn: 118245
* Disable fancy splitting during spilling unless -extra-spiller-splits is given.Jakob Stoklund Olesen2010-11-041-8/+18
| | | | | | | | This way, InlineSpiller does the same amount of splitting as the standard spiller. Splitting should really be guided by the register allocator, and doesn't belong in the spiller at all. llvm-svn: 118216
* Just return undef for invalid masks or elts, and since we're doing that,Eric Christopher2010-11-031-5/+6
| | | | | | just do it earlier too. llvm-svn: 118195
* Let RegAllocBasic require MachineDominators - they are already available andJakob Stoklund Olesen2010-11-031-0/+3
| | | | | | splitting needs them. llvm-svn: 118194
* Tag debug output as regallocJakob Stoklund Olesen2010-11-032-2/+2
| | | | llvm-svn: 118193
* Simplify uses of MVT and EVT. An MVT can be compared directlyDuncan Sands2010-11-032-7/+5
| | | | | | | with a SimpleValueType, while an EVT supports equality and inequality comparisons with SimpleValueType. llvm-svn: 118169
* Inside the calling convention logic LocVT is always a simpleDuncan Sands2010-11-032-18/+18
| | | | | | | | | | value type, so there is no point in passing it around using an EVT. Use the simpler MVT everywhere. Rather than trying to propagate this information maximally in all the code that using the calling convention stuff, I chose to do a mainly low impact change instead. llvm-svn: 118167
* If we have an undef mask our Elt will be -1 for our access, handleEric Christopher2010-11-031-3/+7
| | | | | | | | this by using an undef as a pointer. Fixes rdar://8625016 llvm-svn: 118164
* Fix DAGCombiner to avoid going into an infinite loop when itDan Gohman2010-11-031-1/+36
| | | | | | | encounters (and:i64 (shl:i64 (load:i64), 1), 0xffffffff). This fixes rdar://8606584. llvm-svn: 118143
* Two sets of changes. Sorry they are intermingled.Evan Cheng2010-11-034-30/+56
| | | | | | | | | | | | | 1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to "optimize for latency". Call instructions don't have the right latency and this is more likely to use introduce spills. 2. Fix if-converter cost function. For ARM, it should use instruction latencies, not # of micro-ops since multi-latency instructions is completely executed even when the predicate is false. Also, some instruction will be "slower" when they are predicated due to the register def becoming implicit input. rdar://8598427 llvm-svn: 118135
* Fixes <rdar://problem/8612856>: During postRAsched, the antidependenceAndrew Trick2010-11-022-11/+35
| | | | | | | breaker needs to check all definitions of the antidepenent register to avoid multiple defs of the same new register. llvm-svn: 118032
* Simplify.Devang Patel2010-11-021-2/+1
| | | | llvm-svn: 118027
* If value map does not have register for an argument then try to find frame ↵Devang Patel2010-11-021-5/+8
| | | | | | index before giving up. llvm-svn: 118022
* Use frameindex, if available, as a last resort to emit debug info for a ↵Devang Patel2010-11-021-2/+13
| | | | | | parameter. llvm-svn: 118020
* Don't try to split weird critical edges that really aren't:Jakob Stoklund Olesen2010-11-021-2/+12
| | | | | | | | | | | | | | | BB#1: derived from LLVM BB %bb.nph28 Live Ins: %AL Predecessors according to CFG: BB#0 TEST8rr %reg16384<kill>, %reg16384, %EFLAGS<imp-def>; GR8:%reg16384 JNE_4 <BB#2>, %EFLAGS<imp-use,kill> JMP_4 <BB#2> Successors according to CFG: BB#2 BB#2 These double CFG edges only ever occur in bugpoint-generated code, so there is no need to attempt something clever. llvm-svn: 117992
* MachineLICM should not claim to be preserving the CFG when it can split criticalJakob Stoklund Olesen2010-11-011-1/+0
| | | | | | edges on demand. llvm-svn: 117982
* Be more precise about verifying missing kill flags.Jakob Stoklund Olesen2010-11-011-2/+4
| | | | | | | It is legal for an instruction to have two operands using the same register, only one a kill. This is interpreted as a kill. llvm-svn: 117981
* When inserting copies during splitting, always use the parent register as theJakob Stoklund Olesen2010-11-012-19/+16
| | | | | | | | | | | | source, and let rewrite() clean it up. This way, kill flags on the inserted copies are fixed as well during rewrite(). We can't just assume that all the copies we insert are going to be kills since critical edges into loop headers sometimes require both source and dest to be live out of a block. llvm-svn: 117980
* Add kill flag verification.Jakob Stoklund Olesen2010-11-011-2/+13
| | | | | | | | At least X86FloatingPoint requires correct kill flags after register allocation, and targets using register scavenging benefit. Conservative kill flags are not enough. llvm-svn: 117960
* Update kill flags while rewriting instructions after splitting.Jakob Stoklund Olesen2010-11-011-0/+3
| | | | llvm-svn: 117959
* When we look at instructions to convert to setting the 's' flag, we need to lookBill Wendling2010-11-011-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | at more than those which define CPSR. You can have this situation: (1) subs ... (2) sub r6, r5, r4 (3) movge ... (4) cmp r6, 0 (5) movge ... We cannot convert (2) to "subs" because (3) is using the CPSR set by (1). There's an analogous situation here: (1) sub r1, r2, r3 (2) sub r4, r5, r6 (3) cmp r4, ... (5) movge ... (6) cmp r1, ... (7) movge ... We cannot convert (1) to "subs" because of the intervening use of CPSR. llvm-svn: 117950
* Don't assign new registers created during a split to the same stack slot, butJakob Stoklund Olesen2010-11-013-16/+3
| | | | | | give them individual stack slots once the are actually spilled. llvm-svn: 117945
* Add basic LiveStacks verification.Jakob Stoklund Olesen2010-11-011-0/+20
| | | | | | | When an instruction refers to a spill slot with a LiveStacks entry, check that the spill slot is live at the instruction. llvm-svn: 117944
* The testcase is now XFAILed. Sorry about the breakage.Bill Wendling2010-11-011-0/+2
| | | | llvm-svn: 117904
* Revert r117876 for now, it's causing more testsuite failures.Eric Christopher2010-10-311-2/+0
| | | | llvm-svn: 117879
* Disable the peephole optimizer until 186.crafty on armv6 is fixed. This is whatBill Wendling2010-10-311-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | looks like is happening: Without the peephole optimizer: (1) sub r6, r6, #32 orr r12, r12, lr, lsl r9 orr r2, r2, r3, lsl r10 (x) cmp r6, #0 ldr r9, LCPI2_10 ldr r10, LCPI2_11 (2) sub r8, r8, #32 (a) movge r12, lr, lsr r6 (y) cmp r8, #0 LPC2_10: ldr lr, [pc, r10] (b) movge r2, r3, lsr r8 With the peephole optimizer: ldr r9, LCPI2_10 ldr r10, LCPI2_11 (1*) subs r6, r6, #32 (2*) subs r8, r8, #32 (a*) movge r12, lr, lsr r6 (b*) movge r2, r3, lsr r8 (1) is used by (x) for the conditional move at (a). (2) is used by (y) for the conditional move at (b). After the peephole optimizer, these the flags resulting from (1*) are ignored and only the flags from (2*) are considered for both conditional moves. llvm-svn: 117876
* Attach a GCModuleInfo to a MachineFunction.Nicolas Geoffray2010-10-312-3/+6
| | | | llvm-svn: 117867
* Include MachineBasicBlock numbers in viewCFG() output.Jakob Stoklund Olesen2010-10-301-8/+6
| | | | llvm-svn: 117765
* Make sure copies are inserted after any exception handling labels at the top ofJakob Stoklund Olesen2010-10-301-1/+1
| | | | | | a basic block. llvm-svn: 117764
* Add SkipPHIsAndLabels from PHIElimination to MachineBasicBlock. It is neededJakob Stoklund Olesen2010-10-301-0/+7
| | | | | | elsewhere. llvm-svn: 117763
* Disable more of physical register live intervals verification.Jakob Stoklund Olesen2010-10-301-2/+3
| | | | llvm-svn: 117762
* Print out register class of spilled register.Jakob Stoklund Olesen2010-10-301-2/+4
| | | | llvm-svn: 117761
* Teach machine cse to eliminate instructions with multiple physreg uses and ↵Evan Cheng2010-10-291-50/+45
| | | | | | defs. rdar://8610857. llvm-svn: 117745
* Remove DAG combiner patch to fold vector splats. Instcombiner does it now.Bob Wilson2010-10-291-5/+0
| | | | llvm-svn: 117720
* Fix sign error.Jakob Stoklund Olesen2010-10-291-1/+1
| | | | llvm-svn: 117677
* Avoiding overly aggressive latency scheduling. If the two nodes share anEvan Cheng2010-10-292-24/+78
| | | | | | | | | | | | | | | | | | | | | | | | | operand and one of them has a single use that is a live out copy, favor the one that is live out. Otherwise it will be difficult to eliminate the copy if the instruction is a loop induction variable update. e.g. BB: sub r1, r3, #1 str r0, [r2, r3] mov r3, r1 cmp bne BB => BB: str r0, [r2, r3] sub r3, r3, #1 cmp bne BB This fixed the recent 256.bzip2 regression. llvm-svn: 117675
* Don't transfer unused values to the new intervals formed by splitting.Jakob Stoklund Olesen2010-10-291-0/+3
| | | | llvm-svn: 117673
* Silence Release build warnings.Benjamin Kramer2010-10-291-4/+3
| | | | llvm-svn: 117671
* Teach ConnectedVNInfoEqClasses::Classify to deal with unused values.Jakob Stoklund Olesen2010-10-291-1/+15
| | | | | | | | We don't want unused values forming their own equivalence classes, so we lump them all together in one class, and then merge them with the class of the last used value. llvm-svn: 117670
* Never propagate the idom value out of a block that defines its own value.Jakob Stoklund Olesen2010-10-291-3/+7
| | | | llvm-svn: 117669
* Inline asm multiple alternative constraints development phase 2 - improved ↵John Thompson2010-10-293-47/+77
| | | | | | basic logic, added initial platform support. llvm-svn: 117667
* This may be an ARM target, so check for _Unwind_SjLj_Resume.Bill Wendling2010-10-291-11/+15
| | | | llvm-svn: 117643
* Fix broken equivalence class calculation. We could probably also useJakob Stoklund Olesen2010-10-291-11/+8
| | | | | | | EquvivalenceClasses.h except it looks like overkill when elements are continuous integers. llvm-svn: 117631
OpenPOWER on IntegriCloud