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* Use the presence of the __compact_unwind section to indicate that a targetBill Wendling2011-06-231-10/+7
| | | | | | supports compact unwind info instead of having a separate flag indicating this. llvm-svn: 133685
* Move more logic to shouldTailDuplicate and only duplicate regular bb beforeRafael Espindola2011-06-231-21/+45
| | | | | | | | | | register allocation if it has a indirectbr or if we can duplicate it to every predecessor. This fixes the SingleSource/Benchmarks/Shootout-C++/matrix.cpp regression but keeps the previous improvements to sunspider. llvm-svn: 133682
* Add a flag that indicates whether a target supports compact unwind info or not.Bill Wendling2011-06-221-2/+6
| | | | llvm-svn: 133662
* Reenable tail duplication of bb with just an unconditional jump, butRafael Espindola2011-06-221-4/+4
| | | | | | don't remove blocks that have their address taken. llvm-svn: 133659
* Add a __LD,__compact_unwind section.Bill Wendling2011-06-221-0/+6
| | | | | | | | If the linker supports it, this will hold the CIE and FDE information in a compact format. The implementation of the compact unwinding emission is coming soon. llvm-svn: 133658
* Revert r133607. This is causing failures in the Clang gccTestSuite.Chad Rosier2011-06-221-3/+3
| | | | | | Specifically, gcc.c-torture/compile/pr21356.c. llvm-svn: 133646
* Emit trailing padding on constant vectors when TargetData says that the vectorNick Lewycky2011-06-221-0/+7
| | | | | | is larger than the sum of the elements (including per-element padding). llvm-svn: 133631
* Replace the existing forms of ConstantArray::get() with a single formJay Foad2011-06-222-3/+3
| | | | | | that takes an ArrayRef. llvm-svn: 133615
* Reenable the optimization added in 133415, but change the definition of a ↵Rafael Espindola2011-06-221-3/+3
| | | | | | | | | "simple" bb to be one with only one unconditional branch and no phis. Duplicating the phis in this case is possible, but requeres liveness analysis or breaking edges. llvm-svn: 133607
* After register is spilled there should not be any DBG_VALUE referring the ↵Devang Patel2011-06-211-1/+3
| | | | | | same register. llvm-svn: 133569
* Fix some trailing issues from my introduction of MVT::untyped and its use ↵Owen Anderson2011-06-211-1/+11
| | | | | | for REGISTER_SEQUENCE. llvm-svn: 133567
* Add verbose EH table printing to SjLj exception tables.Bill Wendling2011-06-211-2/+19
| | | | llvm-svn: 133561
* There could be more than one DBG_VALUE instructions for variables where all ↵Devang Patel2011-06-211-4/+6
| | | | | | of them have offset based on one register. llvm-svn: 133560
* Improve the comment printing for the EH table. This gives a much more detailedBill Wendling2011-06-211-23/+69
| | | | | | explanation of what the EH table describes. llvm-svn: 133559
* Teach dag combine to match halfword byteswap patterns.Evan Cheng2011-06-211-2/+264
| | | | | | | | | | | | | | 1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8) => (bswap x) >> 16 2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8)) => (rotl (bswap x) 16) This allows us to eliminate most of the def : Pat patterns for ARM rev16 revsh instructions. It catches many more cases for ARM and x86. rdar://9609108 llvm-svn: 133503
* Disable again.Rafael Espindola2011-06-201-1/+1
| | | | llvm-svn: 133446
* Re enable 133415 with two fixesRafael Espindola2011-06-201-3/+8
| | | | | | | | * Don't introduce a duplicated bb in the CFG * When making a branch unconditional, clear the PredCond array so that it is really unconditional. llvm-svn: 133432
* Disable the logic added by rafael in commit 133415 to see if it brings theDuncan Sands2011-06-201-1/+1
| | | | | | | | dragonegg buildbots back to life. Original commit message: Teach early dup how to duplicate basic blocks with one successor and only phi instructions into more complex blocks. llvm-svn: 133430
* Fix PromoteIntRes_TRUNCATE: Add support for cases where theNadav Rotem2011-06-201-4/+28
| | | | | | | source vector type is to be split while the target vector is to be promoted. (eg: <4 x i64> -> <4 x i8> ) llvm-svn: 133424
* Fix MSVC build. next() function already exists in the MSVC headers. This ↵Francois Pichet2011-06-201-1/+1
| | | | | | create a overload conflict. Make sure we pick up the llvm one. llvm-svn: 133416
* Teach early dup how to duplicate basic blocks with one successor and only ↵Rafael Espindola2011-06-201-2/+142
| | | | | | | | phi instructions into more complex blocks. llvm-svn: 133415
* Revamp the "ConstantStruct::get" methods. Previously, these were scatteredChris Lattner2011-06-201-6/+10
| | | | | | | | | | | | | | | all over the place in different styles and variants. Standardize on two preferred entrypoints: one that takes a StructType and ArrayRef, and one that takes StructType and varargs. In cases where there isn't a struct type convenient, we now add a ConstantStruct::getAnon method (whose name will make more sense after a few more patches land). It would be "really really nice" if the ConstantStruct::get and ConstantVector::get methods didn't make temporary std::vectors. llvm-svn: 133412
* Fix a FIXME by making GlobalVariable::getInitializer() return aJay Foad2011-06-193-7/+7
| | | | | | const Constant *. llvm-svn: 133400
* Code cleanups: Remove duplicated logic in PromotInteRes_BITCAST, reserve ↵Nadav Rotem2011-06-191-7/+5
| | | | | | vector space, reuse types. llvm-svn: 133389
* Calls to AssertZext and getZeroExtendInReg must be made using scalar types.Nadav Rotem2011-06-191-3/+4
| | | | llvm-svn: 133388
* When promoting the vector elements in CopyToParts, use vector truncNadav Rotem2011-06-191-11/+3
| | | | | | instead of scalarizing, and doing an element-by-element truncat. llvm-svn: 133382
* fix the varargs version of StructType::get to not require an LLVMContext, ↵Chris Lattner2011-06-181-2/+1
| | | | | | | | making usage much cleaner. llvm-svn: 133364
* Simplify code. No change in functionality.Benjamin Kramer2011-06-181-6/+1
| | | | llvm-svn: 133350
* Don't allocate empty read-only SmallVectors during SelectionDAG deallocation.Benjamin Kramer2011-06-182-4/+4
| | | | llvm-svn: 133348
* Remove unused but set variables.Benjamin Kramer2011-06-182-19/+4
| | | | llvm-svn: 133347
* Fix UMULO support for 2x register width to allow the fullEric Christopher2011-06-181-0/+21
| | | | | | | | | range without a libcall to a new mulo<mode> libcall that we'd have to create. Finishes the rest of rdar://9090077 and rdar://9210061 llvm-svn: 133318
* Only call TRI::getRawAllocationOrder to resolve a target-dependent hint.Jakob Stoklund Olesen2011-06-171-2/+6
| | | | llvm-svn: 133313
* Fix comment.Eric Christopher2011-06-171-2/+1
| | | | llvm-svn: 133307
* Use the verbose asm flag instead of a new flag for decoding the LSDA.Bill Wendling2011-06-171-4/+1
| | | | llvm-svn: 133292
* Lower multiply with overflow checking to __mulo<mode>Eric Christopher2011-06-173-4/+71
| | | | | | | | | calls if we haven't been able to lower them any other way. Fixes rdar://9090077 and rdar://9210061 llvm-svn: 133288
* Add an option that allows one to "decode" the LSDA.Bill Wendling2011-06-171-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LSDA is a bit difficult for the non-initiated to read. Even with comments, it's not always clear what's going on. This wraps the ASM streamer in a class that retains the LSDA and then emits a human-readable description of what's going on in it. So instead of having to make sense of: Lexception1: .byte 255 .byte 155 .byte 168 .space 1 .byte 3 .byte 26 Lset0 = Ltmp7-Leh_func_begin1 .long Lset0 Lset1 = Ltmp812-Ltmp7 .long Lset1 Lset2 = Ltmp913-Leh_func_begin1 .long Lset2 .byte 3 Lset3 = Ltmp812-Leh_func_begin1 .long Lset3 Lset4 = Leh_func_end1-Ltmp812 .long Lset4 .long 0 .byte 0 .byte 1 .byte 0 .byte 2 .byte 125 .long __ZTIi@GOTPCREL+4 .long __ZTIPKc@GOTPCREL+4 you can read this instead: ## Exception Handling Table: Lexception1 ## @LPStart Encoding: omit ## @TType Encoding: indirect pcrel sdata4 ## @TType Base: 40 bytes ## @CallSite Encoding: udata4 ## @Action Table Size: 26 bytes ## Action 1: ## A throw between Ltmp7 and Ltmp812 jumps to Ltmp913 on an exception. ## For type(s): __ZTIi@GOTPCREL+4 __ZTIPKc@GOTPCREL+4 ## Action 2: ## A throw between Ltmp812 and Leh_func_end1 does not have a landing pad. llvm-svn: 133286
* getSuccWeight returns now default 0 if Weights vector is empty.Jakub Staszak2011-06-171-2/+4
| | | | llvm-svn: 133271
* Allow empty Weights vector.Jakub Staszak2011-06-171-1/+2
| | | | llvm-svn: 133265
* Two fixes relating to debug value:Rafael Espindola2011-06-171-0/+10
| | | | | | | | * We should change the generated code because of a debug use. * Avoid creating debug uses of undef, as they become a kill. Test to follow. llvm-svn: 133255
* Add a hook for PBQP clients to run a custom pre-alloc pass to run prior to ↵Lang Hames2011-06-171-4/+9
| | | | | | PBQP allocation. Patch by Arnaud Allard de Grandmaison. llvm-svn: 133249
* Enable early duplication of small blocks. There are still improvements toRafael Espindola2011-06-171-29/+32
| | | | | | be made, but this is already a win. llvm-svn: 133240
* Rename TRI::getAllocationOrder() to getRawAllocationOrder().Jakob Stoklund Olesen2011-06-162-17/+15
| | | | | | | | | | | Also switch the return type to ArrayRef<unsigned> which works out nicely for ARM's implementation of this function because of the clever ArrayRef constructors. The name change indicates that the returned allocation order may contain reserved registers as has been the case for a while. llvm-svn: 133216
* Don't use register classes larger than TLI->getRegClassFor(VT).Jakob Stoklund Olesen2011-06-161-2/+7
| | | | | | | | | | In Thumb mode we cannot handle GPR virtual registers, even though some instructions can. When isel is lowering a CopyFromReg, it should limit itself to subclasses of getRegClassFor(VT). <rdar://problem/9624323> llvm-svn: 133210
* Teach antidependency breakers to use RegisterClassInfo.Jakob Stoklund Olesen2011-06-165-33/+39
| | | | | | No functional change was intended. llvm-svn: 133202
* Move PBQP off allocation_order_begin. No functional change intended.Jakob Stoklund Olesen2011-06-161-5/+4
| | | | | | | I think PBQP could use RegisterClassInfo, but it didn't fit neatly with the external interfaces that PBQP uses, so I'll leave that to Lang. llvm-svn: 133186
* Introduce MachineBranchProbabilityInfo class, which has similar API toJakub Staszak2011-06-166-18/+233
| | | | | | | | BranchProbabilityInfo (expect setEdgeWeight which is not available here). Branch Weights are kept in MachineBasicBlocks. To turn off this analysis set -use-mbpi=false. llvm-svn: 133184
* Change the REG_SEQUENCE SDNode to take an explict register class ID as its ↵Owen Anderson2011-06-161-5/+6
| | | | | | | | first operand. This operand is lowered away by the time we reach MachineInstrs, so the actual register-allocation handling of them doesn't need to change. This is intended to support using REG_SEQUENCE SDNode's with type MVT::untyped, and is part of the long road to eliminating some of the hacks we currently use to support register pairs and other strange constraints, particularly on ARM NEON. llvm-svn: 133178
* Switch linear scan to using RegisterClassInfo.Jakob Stoklund Olesen2011-06-161-18/+12
| | | | | | | | | This avoids the manual filtering of reserved registers and removes the dependency on allocation_order_begin(). Palliative care... llvm-svn: 133177
* Test commit.Jakub Staszak2011-06-161-7/+7
| | | | llvm-svn: 133174
* Add TargetRegisterInfo::getRawAllocationOrder().Jakob Stoklund Olesen2011-06-163-18/+21
| | | | | | | | | | | | | This virtual function will replace allocation_order_begin/end as the one to override when implementing custom allocation orders. It is simpler to have one function return an ArrayRef than having two virtual functions computing different ends of the same array. Use getRawAllocationOrder() in place of allocation_order_begin() where it makes sense, but leave some clients that look like they really want the filtered allocation orders from RegisterClassInfo. llvm-svn: 133170
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