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* Fix cycle in selection DAG introduced by extractelement legalizationRobert Lougher2015-12-091-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | During selection DAG legalization, extractelement is replaced with a load instruction. To do this, a temporary store to the stack is used unless an existing store is found that can be re-used. If re-using a store, the chain going out of the store must be replaced by the one going out of the new load (this ensures that any stores that must take place after the store happens after the load, else the value might be overwritten before it is loaded). The problem is, if the extractelement index is dependent on the store replacing the chain will introduce a cycle in the selection DAG (the load uses the index, and by replacing the chain we will make the index dependent on the load). To fix this, if the index is dependent on the store, the store is skipped. This is conservative as we may end up creating an unnecessary extra store to the stack. However, the situation is not expected to occur very often. Differential Revision: http://reviews.llvm.org/D15330 llvm-svn: 255114
* Revert "Implement a new pass - LiveDebugValues - to compute the set of live ↵Mehdi Amini2015-12-094-405/+0
| | | | | | | | | | | DEBUG_VALUEs at each basic block and insert them. Reviewed and accepted at: http://reviews.llvm.org/D11933" This reverts commit r255096. Break the bots: http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-incremental_check/16378/ From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 255101
* Implement a new pass - LiveDebugValues - to compute the set of live ↵Vikram TV2015-12-094-0/+405
| | | | | | DEBUG_VALUEs at each basic block and insert them. Reviewed and accepted at: http://reviews.llvm.org/D11933 llvm-svn: 255096
* [CGP] Reimplement r255055 a different wayReid Kleckner2015-12-081-0/+4
| | | | llvm-svn: 255070
* Revert "[CGP] Check that we have an insert point before moving ↵Reid Kleckner2015-12-081-8/+4
| | | | | | | | | | llvm.dbg.value around" This reverts commit r255055. Breakage has been reported. llvm-svn: 255063
* [CGP] Check that we have an insert point before moving llvm.dbg.value aroundReid Kleckner2015-12-081-4/+8
| | | | llvm-svn: 255055
* AsmPrinter: Use emitGlobalConstantFP to emit elements of constant dataJustin Bogner2015-12-081-16/+4
| | | | | | | | | | It's strange to duplicate the logic for emitting FP values into emitGlobalConstantDataSequential, and it's even stranger that we end up printing the verbose assembly comments differently between the two paths. Just call into emitGlobalConstantFP rather than crudely duplicating its logic. llvm-svn: 254988
* fix return values to match bool return type; NFC Sanjay Patel2015-12-071-2/+2
| | | | llvm-svn: 254968
* AVX-512: Fixed masked load / store instruction selection for KNL.Elena Demikhovsky2015-12-071-1/+4
| | | | | | | | | | | | | | | Patterns were missing for KNL target for <8 x i32>, <8 x float> masked load/store. This intrinsic comes with all legal types: <8 x float> @llvm.masked.load.v8f32(<8 x float>* %addr, i32 align, <8 x i1> %mask, <8 x float> %passThru), but still requires lowering, because VMASKMOVPS, VMASKMOVDQU32 work with 512-bit vectors only. All data operands should be widened to 512-bit vector. The mask operand should be widened to v16i1 with zeroes. Differential Revision: http://reviews.llvm.org/D15265 llvm-svn: 254909
* Replace uint16_t with the MCPhysReg typedef in many places. A lot of ↵Craig Topper2015-12-054-12/+14
| | | | | | physical register arrays already use this typedef. llvm-svn: 254843
* Normalize successors' probabilities when building MBBs for jump table.Cong Hou2015-12-051-0/+2
| | | | llvm-svn: 254837
* ScheduleDAGInstrs: Move LiveIntervals field to ScheduleDAGMIMatthias Braun2015-12-041-2/+1
| | | | | | | Now that ScheduleDAGInstrs doesn't need it anymore we can move the field down the class hierarcy to ScheduleDAGMI. llvm-svn: 254759
* Revert "[BranchFolding] Merge MMOs during tail merge"Rafael Espindola2015-12-041-26/+16
| | | | | | | | This reverts commit r254694. It broke bootstrap. llvm-svn: 254700
* [BranchFolding] Merge MMOs during tail mergeJunmo Park2015-12-041-16/+26
| | | | | | | | | | | | | | | | | Summary: If we remove the MMOs from Load/Store instructions, they are treated as volatile. This makes other optimization passes unhappy. eg. Load/Store Optimization So, it looks better to merge, not remove. Reviewers: gberry, mcrosier Subscribers: gberry, llvm-commits Differential Revision: http://reviews.llvm.org/D14797 llvm-svn: 254694
* (no commit message)Junmo Park2015-12-041-1/+1
| | | | llvm-svn: 254686
* ScheduleDAGInstrs: Rework schedule graph builder.Matthias Braun2015-12-041-66/+161
| | | | | | | | | | | | | | | | | | Re-comitting with a change that avoids undefined uses getting put into the VRegUses list. The new algorithm remembers the uses encountered while walking backwards until a matching def is found. Contrary to the previous version this: - Works without LiveIntervals being available - Allows to increase the precision to subregisters/lanemasks (not used for now) The changes in the AMDGPU tests are necessary because the R600 scheduler is not stable with respect to the order of nodes in the ready queues. Differential Revision: http://reviews.llvm.org/D9068 llvm-svn: 254683
* raw_ostream: << operator for callables with raw_ostream argumentMatthias Braun2015-12-043-76/+64
| | | | | | | | | This is a revised version of r254655 which uses a Printable wrapper class to avoid ambiguous overload problems. Differential Revision: http://reviews.llvm.org/D14348 llvm-svn: 254681
* Emit function alias to data as a function symbol.Evgeniy Stepanov2015-12-041-0/+5
| | | | | | | | | | CFI emits jump slots for indirect functions as a byte array constant, and declares function-typed aliases to these constants. This change fixes AsmPrinter to emit these aliases as function symbols and not data symbols. llvm-svn: 254674
* CodeGen peephole: fold redundant phys reg copiesJF Bastien2015-12-031-12/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Code generation often exposes redundant physical register copies through virtual registers such as: %vreg = COPY %PHYSREG ... %PHYSREG = COPY %vreg There are cases where no intervening clobber of %PHYSREG occurs, and the later copy could therefore be removed. In some cases this further allows us to remove the initial copy. This patch contains a motivating example which comes from the x86 build of Chrome, specifically cc::ResourceProvider::UnlockForRead uses libstdc++'s implementation of hash_map. That example has two tests live at the same time, and after machine sinking LLVM has confused itself enough and things spilling EFLAGS is a great idea even though it's never restored and the comparison results are both live. Before this patch we have: DEC32m %RIP, 1, %noreg, <ga:@L>, %noreg, %EFLAGS<imp-def> %vreg1<def> = COPY %EFLAGS; GR64:%vreg1 %EFLAGS<def> = COPY %vreg1; GR64:%vreg1 JNE_1 <BB#1>, %EFLAGS<imp-use> Both copies are useless. This patch tries to eliminate the later copy in a generic manner. dec is especially confusing to LLVM when compared with sub. I wrote this patch to treat all physical registers generically, but only remove redundant copies of non-allocatable physical registers because the allocatable ones caused issues (e.g. when calling conventions weren't properly modeled) and should be handled later by the register allocator anyways. The following tests used to failed when the patch also replaced allocatable registers: CodeGen/X86/StackColoring.ll CodeGen/X86/avx512-calling-conv.ll CodeGen/X86/copy-propagation.ll CodeGen/X86/inline-asm-fpstack.ll CodeGen/X86/musttail-varargs.ll CodeGen/X86/pop-stack-cleanup.ll CodeGen/X86/preserve_mostcc64.ll CodeGen/X86/tailcallstack64.ll CodeGen/X86/this-return-64.ll This happens because COPY has other special meaning for e.g. dependency breakage and x87 FP stack. Note that all other backends' tests pass. Reviewers: qcolombet Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D15157 llvm-svn: 254665
* AsmPrinter: Simplify emitting FP elements in sequential data. NFCJustin Bogner2015-12-031-26/+15
| | | | | | | Use APFloat APIs here Rather than manually type-punning through unions. llvm-svn: 254664
* Revert "raw_ostream: << operator for callables with raw_stream argument"Matthias Braun2015-12-033-62/+76
| | | | | | | | This commit provoked "error C2593: 'operator <<' is ambiguous" on MSVC. This reverts commit r254655. llvm-svn: 254661
* raw_ostream: << operator for callables with raw_stream argumentMatthias Braun2015-12-033-76/+62
| | | | | | | | | | | | | | | | | This allows easier construction of print helpers. Example: Printable PrintLaneMask(unsigned LaneMask) { return Printable([LaneMask](raw_ostream &OS) { OS << format("%08X", LaneMask); }); } // Usage: OS << PrintLaneMask(Mask); Differential Revision: http://reviews.llvm.org/D14348 llvm-svn: 254655
* [X86] Part 1 to fix x86-64 fp128 calling convention.Chih-Hung Hsieh2015-12-0312-74/+277
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Almost all these changes are conditioned and only apply to the new x86-64 f128 type configuration, which will be enabled in a follow up patch. They are required together to make new f128 work. If there is any error, we should fix or revert them as a whole. These changes should have no impact to current configurations. * Relax type legalization checks to accept new f128 type configuration, whose TypeAction is TypeSoftenFloat, not TypeLegal, but also has TLI.isTypeLegal true. * Relax GetSoftenedFloat to return in some cases f128 type SDValue, which is TLI.isTypeLegal but not "softened" to i128 node. * Allow customized FABS, FNEG, FCOPYSIGN on new f128 type configuration, to generate optimized bitwise operators for libm functions. * Enhance related Lower* functions to handle f128 type. * Enhance DAGTypeLegalizer::run, SoftenFloatResult, and related functions to keep new f128 type in register, and convert f128 operators to library calls. * Fix Combiner, Emitter, Legalizer routines that did not handle f128 type. * Add ExpandConstant to handle i128 constants, ExpandNode to handle ISD::Constant node. * Add one more parameter to getCommonSubClass and firstCommonClass, to guarantee that returned common sub class will contain the specified simple value type. This extra parameter is used by EmitCopyFromReg in InstrEmitter.cpp. * Fix infinite loop in getTypeLegalizationCost when f128 is the value type. * Fix printOperand to handle null operand. * Enhance ISD::BITCAST node to handle f128 constant. * Expand new f128 type for BR_CC, SELECT_CC, SELECT, SETCC nodes. * Enhance X86AsmPrinter to emit f128 values in comments. Differential Revision: http://reviews.llvm.org/D15134 llvm-svn: 254653
* [WinEH] Avoid infinite loop in BranchFolding for multiple single block funcletsAndrew Kaylor2015-12-031-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D14996 llvm-svn: 254629
* Revert "ScheduleDAGInstrs: Rework schedule graph builder."Matthias Braun2015-12-031-159/+66
| | | | | | | | | | This works mostly fine but breaks some stage 1 builders when compiling compiler-rt on i386. Revert for further investigation as I can't see an obvious cause/fix. This reverts commit r254577. llvm-svn: 254586
* ScheduleDAGInstrs: Rework schedule graph builder.Matthias Braun2015-12-031-66/+159
| | | | | | | | | | | | | | | The new algorithm remembers the uses encountered while walking backwards until a matching def is found. Contrary to the previous version this: - Works without LiveIntervals being available - Allows to increase the precision to subregisters/lanemasks (not used for now) The changes in the AMDGPU tests are necessary because the R600 scheduler is not stable with respect to the order of nodes in the ready queues. Differential Revision: http://reviews.llvm.org/D9068 llvm-svn: 254577
* RegisterPressure: Use range based for, fix else style; NFCMatthias Braun2015-12-031-41/+28
| | | | llvm-svn: 254575
* Move EH-specific helper functions to a more appropriate placeDavid Majnemer2015-12-026-6/+6
| | | | | | No functionality change is intended. llvm-svn: 254562
* Use std::string instead of strdup() and free() in WinCodeViewLineTablesReid Kleckner2015-12-022-15/+6
| | | | llvm-svn: 254557
* [CodeGen]: Fix bad interaction with AntiDep breaking and inline asm.Kyle Butt2015-12-021-3/+6
| | | | | | | | | AggressiveAntiDepBreaker was renaming registers specified by the user for inline assembly. While this will work for compiler-specified registers, it won't work for user-specified registers, and at the time this runs, I don't currently see a way to distinguish them. llvm-svn: 254532
* Fix accidental off by one changeFiona Glaser2015-12-021-1/+1
| | | | | | Didn't break any tests, but did unnecessary extra work. llvm-svn: 254529
* Scheduler / Regalloc: use unique_ptr[] instead of std::vectorFiona Glaser2015-12-022-15/+16
| | | | | | | | | vector.resize() is significantly slower than memset in many STLs and the cost of initializing these vectors is significant on targets with many registers. Since we don't need the overhead of a vector, use a simple unique_ptr instead. llvm-svn: 254526
* AArch64: use ldxp/stxp pair to implement 128-bit atomic loads.Tim Northover2015-12-021-30/+38
| | | | | | | | The ARM ARM is clear that 128-bit loads are only guaranteed to have been atomic if there has been a corresponding successful stxp. It's less clear for AArch32, so I'm leaving that alone for now. llvm-svn: 254524
* Fix a bug in IfConversion.cpp.Cong Hou2015-12-011-3/+2
| | | | | | | | The bug is introduced in r254377 which failed some tests on ARM, where a new probability is assigned to a successor but the provided BB may not be a successor. llvm-svn: 254463
* use range-based for loops; NFCISanjay Patel2015-12-011-12/+6
| | | | llvm-svn: 254453
* don't repeat function/variable names in comments; NFCSanjay Patel2015-12-011-64/+57
| | | | llvm-svn: 254445
* fix typo; NFCSanjay Patel2015-12-011-1/+1
| | | | llvm-svn: 254442
* Fixed a failure in cost calculation for vector GEPElena Demikhovsky2015-12-011-8/+8
| | | | | | | | | Cost calculation for vector GEP failed with due to invalid cast to GEP index operand. The bug is fixed, added a test. http://reviews.llvm.org/D14976 llvm-svn: 254408
* Introduce new @llvm.get.dynamic.area.offset.i{32, 64} intrinsics.Yury Gribov2015-12-015-0/+34
| | | | | | | | | | | | | | | The @llvm.get.dynamic.area.offset.* intrinsic family is used to get the offset from native stack pointer to the address of the most recent dynamic alloca on the caller's stack. These intrinsics are intendend for use in combination with @llvm.stacksave and @llvm.restore to get a pointer to the most recent dynamic alloca. This is useful, for example, for AddressSanitizer's stack unpoisoning routines. Patch by Max Ostapenko. Differential Revision: http://reviews.llvm.org/D14983 llvm-svn: 254404
* Allow known and unknown probabilities coexist in MBB's successor list.Cong Hou2015-12-011-8/+17
| | | | | | | | | | Previously it is not allowed for each MBB to have successors with both known and unknown probabilities. However, this may be too strict as at this stage we could not always guarantee that. It is better to remove this restriction now, and I will work on validating MBB's successors' probabilities first (for example, check if the sum is approximate one). llvm-svn: 254402
* Replace all weight-based interfaces in MBB with probability-based ↵Cong Hou2015-12-018-303/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | interfaces, and update all uses of old interfaces. (This is the second attempt to submit this patch. The first caused two assertion failures and was reverted. See https://llvm.org/bugs/show_bug.cgi?id=25687) The patch in http://reviews.llvm.org/D13745 is broken into four parts: 1. New interfaces without functional changes (http://reviews.llvm.org/D13908). 2. Use new interfaces in SelectionDAG, while in other passes treat probabilities as weights (http://reviews.llvm.org/D14361). 3. Use new interfaces in all other passes. 4. Remove old interfaces. This patch is 3+4 above. In this patch, MBB won't provide weight-based interfaces any more, which are totally replaced by probability-based ones. The interface addSuccessor() is redesigned so that the default probability is unknown. We allow unknown probabilities but don't allow using it together with known probabilities in successor list. That is to say, we either have a list of successors with all known probabilities, or all unknown probabilities. In the latter case, we assume each successor has 1/N probability where N is the number of successors. An assertion checks if the user is attempting to add a successor with the disallowed mixed use as stated above. This can help us catch many misuses. All uses of weight-based interfaces are now updated to use probability-based ones. Differential revision: http://reviews.llvm.org/D14973 llvm-svn: 254377
* RegisterPressure: If we do not collect dead defs the list must be emptyMatthias Braun2015-12-011-5/+1
| | | | llvm-svn: 254372
* RegisterPressure: Remove support for recede()/advance() at MBB boundariesMatthias Braun2015-12-011-18/+5
| | | | | | | Nobody was checking the returnvalue of recede()/advance() so we can simply replace this code with asserts. llvm-svn: 254371
* RegisterPressure: Split RegisterOperands analysis code from result object; NFCMatthias Braun2015-12-011-43/+60
| | | | | | | This is in preparation to expose the RegisterOperands class as RegisterPressure API. llvm-svn: 254368
* Revert r254348: "Replace all weight-based interfaces in MBB with ↵Hans Wennborg2015-12-018-171/+301
| | | | | | | | | | probability-based interfaces, and update all uses of old interfaces." and the follow-up r254356: "Fix a bug in MachineBlockPlacement that may cause assertion failure during BranchProbability construction." Asserts were firing in Chromium builds. See PR25687. llvm-svn: 254366
* Fix a bug in MachineBlockPlacement that may cause assertion failure during ↵Cong Hou2015-12-011-3/+7
| | | | | | | | BranchProbability construction. The root cause is the rounding behavior in BranchProbability construction. We may consider to use truncation instead in the future. llvm-svn: 254356
* Extend debug info for function parameters in SDAG.Evgeniy Stepanov2015-12-011-16/+11
| | | | | | | | | | | | | SDAG currently can emit debug location for function parameters when an llvm.dbg.declare points to either a function argument SSA temp, or to an AllocaInst. This change extends this logic by adding a fallback case when neither of the above is true. This is required for SafeStack, which may copy the contents of a byval function argument into something that is not an alloca, and then describe the target as the new location of the said argument. llvm-svn: 254352
* Replace all weight-based interfaces in MBB with probability-based ↵Cong Hou2015-12-018-301/+167
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | interfaces, and update all uses of old interfaces. The patch in http://reviews.llvm.org/D13745 is broken into four parts: 1. New interfaces without functional changes (http://reviews.llvm.org/D13908). 2. Use new interfaces in SelectionDAG, while in other passes treat probabilities as weights (http://reviews.llvm.org/D14361). 3. Use new interfaces in all other passes. 4. Remove old interfaces. This patch is 3+4 above. In this patch, MBB won't provide weight-based interfaces any more, which are totally replaced by probability-based ones. The interface addSuccessor() is redesigned so that the default probability is unknown. We allow unknown probabilities but don't allow using it together with known probabilities in successor list. That is to say, we either have a list of successors with all known probabilities, or all unknown probabilities. In the latter case, we assume each successor has 1/N probability where N is the number of successors. An assertion checks if the user is attempting to add a successor with the disallowed mixed use as stated above. This can help us catch many misuses. All uses of weight-based interfaces are now updated to use probability-based ones. Differential revision: http://reviews.llvm.org/D14973 llvm-svn: 254348
* Have 'optnone' respect the -fast-isel=false option.Paul Robinson2015-11-302-4/+9
| | | | | | | | This is primarily useful for debugging optnone v. ISel issues. Differential Revision: http://reviews.llvm.org/D14792 llvm-svn: 254335
* Use a lambda instead of std::bind and std::mem_fn I introduced in r254242. NFCCraig Topper2015-11-291-2/+3
| | | | llvm-svn: 254260
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