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* Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng2012-02-285-20/+29
| | | | | | | | | | | | | | | | | the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 llvm-svn: 151623
* Handle regmasks in MachineCSE.Jakob Stoklund Olesen2012-02-281-0/+6
| | | | | | | | Don't attempt to extend physreg live ranges across calls. <rdar://problem/10942095> llvm-svn: 151610
* Handle regmasks in the machine code verifier.Jakob Stoklund Olesen2012-02-281-0/+15
| | | | llvm-svn: 151607
* Fix 80-column violation.Chad Rosier2012-02-281-2/+2
| | | | llvm-svn: 151599
* Fix for PR12090: clear def maps of aliases when visiting a copy. e.g.Evan Cheng2012-02-271-0/+5
| | | | | | | | | %S5<def> = COPY %S0<kill> First clear def map of Q1, etc. No small test case available. llvm-svn: 151574
* Update machine code verifier.Jakob Stoklund Olesen2012-02-271-35/+91
| | | | | | | | | After the SlotIndex slot names were updated, it is possible to apply stricter checks to live intervals. Also treat bundles as bags of operands when checking live intervals. llvm-svn: 151531
* Make the peephole optimizer clear kill flags on a vreg if it's about to add newLang Hames2012-02-251-0/+4
| | | | | | | | | uses of the vreg, since the old kills may no longer be valid. This was causing -verify-machineinstrs to complain about uses after kills, and could potentially have been causing subtle register allocation issues, but I haven't come across a test case yet. llvm-svn: 151425
* Fixed typo.Lang Hames2012-02-251-1/+1
| | | | llvm-svn: 151417
* Add missing staticJakob Stoklund Olesen2012-02-241-3/+3
| | | | llvm-svn: 151396
* Add a -stress-regalloc=<N> option.Jakob Stoklund Olesen2012-02-241-1/+9
| | | | | | | This will limit all register classes to N registers in order to stress test register allocation. llvm-svn: 151379
* Don't crash when a glue node contains an internal CopyToRegHal Finkel2012-02-241-0/+3
| | | | | | | This is necessary to support the existing ppc lowering code for indirect calls. Fixes PR12071. llvm-svn: 151373
* SDAGBuilder: Remove register sets that were never read and prune dead code ↵Benjamin Kramer2012-02-241-63/+3
| | | | | | surrounding it. llvm-svn: 151364
* ScheduleDAGInstrs.h:155: warning: suggest parentheses around `&&' within `||'.Nick Lewycky2012-02-241-1/+1
| | | | llvm-svn: 151355
* PostRA sched: speed up physreg tracking by not abusing SparseSet.Andrew Trick2012-02-242-35/+80
| | | | llvm-svn: 151348
* Turn avx insert intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove ↵Pete Cooper2012-02-241-0/+15
| | | | | | duplicate patterns for selecting the intrinsics llvm-svn: 151342
* If the Address of a variable is an argument then treat the entireEric Christopher2012-02-241-3/+7
| | | | | | | | | | | variable declaration as an argument because we want that address anyhow for our debug information. This seems to fix rdar://9965111, at least we have more debug information than before and from reading the assembly it appears to be the correct location. llvm-svn: 151335
* Tabs, formatting and long lines oh my!Eric Christopher2012-02-241-4/+6
| | | | llvm-svn: 151334
* Allow an integer to be converted into an MMX type when it's used in an inlineBill Wendling2012-02-231-2/+8
| | | | | | | asm. <rdar://problem/10106006> llvm-svn: 151303
* BitVectorize loop.Benjamin Kramer2012-02-231-3/+1
| | | | llvm-svn: 151274
* post-ra-sched: Turn the KillIndices vector into a bitvector, it only stored ↵Benjamin Kramer2012-02-231-28/+22
| | | | | | | | two meaningful states. Rename it to LiveRegs to make it more clear what's stored inside. llvm-svn: 151273
* post-ra-sched: Replace a std::set of regs with a bitvector.Benjamin Kramer2012-02-231-5/+4
| | | | | | | | | Assuming that a single std::set node adds 3 control words, a bitvector can store (3*8+4)*8=224 registers in the allocated memory of a single element in the std::set (x86_64). Also we don't have to call malloc for every register added. llvm-svn: 151269
* Make calls scheduling boundaries post-ra.Jakob Stoklund Olesen2012-02-231-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before register allocation, instructions can be moved across calls in order to reduce register pressure. After register allocation, we don't gain a lot by moving callee-saved defs across calls. In fact, since the scheduler doesn't have a good idea how registers are used in the callee, it can't really make good scheduling decisions. This changes the schedule in two ways: 1. Latencies to call uses and defs are no longer accounted for, causing some random shuffling around calls. This isn't really a problem since those uses and defs are inaccurate proxies for what happens inside the callee. They don't represent registers used by the call instruction itself. 2. Instructions are no longer moved across calls. This didn't happen very often, and the scheduling decision was made on dubious information anyway. As with any scheduling change, benchmark numbers shift around a bit, but there is no positive or negative trend from this change. This makes the post-ra scheduler 5% faster for ARM targets. The secret motivation for this patch is the introduction of register mask operands representing call clobbers. The most efficient way of handling regmasks in ScheduleDAGInstrs is to model them as barriers for physreg live ranges, but not for virtreg live ranges. That's fine pre-ra, but post-ra it would have the same effect as this patch. llvm-svn: 151265
* Strip a layer of boilerplate from the VLIWPacketizer by storing the ↵Benjamin Kramer2012-02-231-18/+8
| | | | | | scheduler as an opaque pointer. llvm-svn: 151252
* Fix to make sure that a comdat group gets generated correctly for a static ↵Anton Korobeynikov2012-02-231-1/+2
| | | | | | | | | | member of instantiated C++ templates. Patch by Kristof Beyls! llvm-svn: 151250
* More newline cleanups.Eric Christopher2012-02-232-4/+4
| | | | llvm-svn: 151235
* Add some handy-dandy newlines.Eric Christopher2012-02-231-2/+2
| | | | llvm-svn: 151234
* misched: cleanup reaching def computationAndrew Trick2012-02-231-3/+5
| | | | | | | | Ignore undef uses completely. Use a more explicit SlotIndex API. Add more explicit comments. llvm-svn: 151233
* PostRASched: Convert physreg def/use tracking to Jakob's SparseSet.Andrew Trick2012-02-232-84/+104
| | | | | | | Added array subscript to SparseSet for convenience. Slight reorg to make it easier to manage the def/use sets. llvm-svn: 151228
* Handle regmasks in FixupKills.Jakob Stoklund Olesen2012-02-231-0/+4
| | | | llvm-svn: 151226
* Handle regmasks in CriticalAntiDepBreaker.Jakob Stoklund Olesen2012-02-231-0/+14
| | | | llvm-svn: 151223
* Track reserved registers separately from RegsAvailable.Jakob Stoklund Olesen2012-02-231-5/+4
| | | | | | | The bulk masking operations from register mask operands don't account for reserved registers. llvm-svn: 151222
* Don't compute latencies for regmask operands.Jakob Stoklund Olesen2012-02-221-1/+3
| | | | llvm-svn: 151211
* Handle regmasks in RegisterScavenging.Jakob Stoklund Olesen2012-02-221-0/+4
| | | | llvm-svn: 151210
* misched: Use SparseSet for VRegDegs for constant time clear().Andrew Trick2012-02-222-16/+41
| | | | llvm-svn: 151205
* Allow the use of an alternate symbol for calculating a function's size.Hal Finkel2012-02-221-1/+4
| | | | | | | | | | | | | The standard function epilog includes a .size directive, but ppc64 uses an alternate local symbol to tag the actual start of each function. Until recently, binutils accepted the .size directive as: .size test1, .Ltmp0-test1 however, using this directive with recent binutils will result in the error: .size expression for XXX does not evaluate to a constant so we must use the label which actually tags the start of the function. llvm-svn: 151200
* Properly emit _fltused with FastISel. Refactor to share code with SDAG.Michael J. Spencer2012-02-224-17/+30
| | | | | | Patch by Joe Groff! llvm-svn: 151183
* Comment from code reviewAndrew Trick2012-02-221-0/+1
| | | | llvm-svn: 151178
* Remove extra semi-colons.Chad Rosier2012-02-221-2/+2
| | | | llvm-svn: 151169
* 80 col.Jakob Stoklund Olesen2012-02-221-3/+5
| | | | llvm-svn: 151167
* Only add DW_AT_prototyped if we're working with a C-like language.Eric Christopher2012-02-221-3/+12
| | | | | | | | Worth another 45k (1%) off of a large C++ testcase. rdar://10909458 llvm-svn: 151144
* Add the source language into the compile unit.Eric Christopher2012-02-223-4/+10
| | | | llvm-svn: 151143
* Remove extra semi-colon.Eric Christopher2012-02-221-1/+1
| | | | llvm-svn: 151142
* misched: DAG builder should not track dependencies for SSA defs.Andrew Trick2012-02-221-1/+5
| | | | | | | The vast majority of virtual register definitions don't need an entry in the DAG builder's VRegDefs set. llvm-svn: 151136
* Initialize SUnits before DAG building.Andrew Trick2012-02-225-75/+113
| | | | | | | | | | | | Affect on SD scheduling and postRA scheduling: Printing the DAG will display the nodes in top-down topological order. This matches the order within the MBB and makes my life much easier in general. Affect on misched: We don't need to track virtual register uses at all. This is awesome. I also intend to rely on the SUnit ID as a topo-sort index. So if A < B then we cannot have an edge B -> A. llvm-svn: 151135
* Make all pointers to TargetRegisterClass const since they are all pointers ↵Craig Topper2012-02-222-5/+5
| | | | | | to static data that should not be modified. llvm-svn: 151134
* Use SparseSet for the RAFast live virtual register map.Jakob Stoklund Olesen2012-02-221-73/+110
| | | | | | | | | | | | This makes RAFast 4% faster, and it gets rid of the dodgy DenseMap iteration. This also revealed that RAFast would sometimes dereference DenseMap iterators after erasing other elements from the map. That does seem to work in the current DenseMap implementation, but SparseSet doesn't allow it. llvm-svn: 151111
* Add API "handleMoveIntoBundl" for updating liveness when moving instructions ↵Lang Hames2012-02-211-13/+68
| | | | | | | | | | | | into bundles. This method takes a bundle start and an MI being bundled, and makes the intervals for the MI's operands appear to start/end on the bundle start. Also fixes some minor cosmetic issues (whitespace, naming convention) in the HMEditor code. llvm-svn: 151099
* There's no need for a DW_AT_byte_size on a pointer type.Eric Christopher2012-02-211-1/+1
| | | | | | Part of rdar://10493979 where it reduces by about .5% (10k) llvm-svn: 151097
* Clear virtual registers after they are no longer referenced.Andrew Trick2012-02-217-5/+39
| | | | | | | | | | | | | Passes after RegAlloc should be able to rely on MRI->getNumVirtRegs() == 0. This makes sharing code for pre/postRA passes more robust. Now, to check if a pass is running before the RA pipeline begins, use MRI->isSSA(). To check if a pass is running after the RA pipeline ends, use !MRI->getNumVirtRegs(). PEI resets virtual regs when it's done scavenging. PTX will either have to provide its own PEI pass or assign physregs. llvm-svn: 151032
* StackSlotColoring does not use a VirtRegMapAndrew Trick2012-02-211-4/+0
| | | | llvm-svn: 151031
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