| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 152153
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llvm-svn: 152089
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providing a default expansion (FADD+FNEG), and teaching DAGCombine not to form FSUBs post-legalize if they are not legal.
llvm-svn: 152079
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Used to allow context sensitive printing of super-register or sub-register
references.
llvm-svn: 152043
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Patch by Sean Silva!
llvm-svn: 152042
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static data size.
llvm-svn: 152016
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The first def of a virtual register cannot also read the register.
Assert on such bad machine code instead of trying to fix it.
TwoAddressInstructionPass should never create code like that.
llvm-svn: 152010
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We are already setting <undef> flags, and that is good enough. The
<imp-def> operands don't mean anything any more.
llvm-svn: 152009
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llvm-svn: 152001
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static data size.
llvm-svn: 151998
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size of static data.
llvm-svn: 151996
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llvm-svn: 151875
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llvm-svn: 151874
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to the string table for the function name, not the function name.
llvm-svn: 151873
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The inline table needs to be constructed ahead of time so that it doesn't try to
create new strings while we're emitting everything.
This reverts commit a8ff9bccb399183cdd5f1c3cec2bda763664b4b0.
llvm-svn: 151864
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fixups that are being used to determine section offsets. Reduces
the total number of fixups by 50% for a non-trivial testcase.
Part of rdar://10413936
llvm-svn: 151852
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llvm-svn: 151849
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though they could have sideeffects.
Only allow log2/exp2 to be converted to an intrinsic if they are declared "readnone".
llvm-svn: 151807
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Simply treat bundles as instructions. Spill code is inserted between
bundles, never inside a bundle. Rewrite all operands in a bundle at
once.
Don't attempt and memory operand folding inside bundles.
llvm-svn: 151787
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This allows the function to be inlined, and makes it suitable for use in
getInstructionIndex().
Also provide a const version. C++ is great for touch typing practice.
llvm-svn: 151782
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While we're at it - don't copy vreg implicit operands while rematerializing.
This fixes PR12138.
llvm-svn: 151779
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optimization, making the lives of later passes easier.
llvm-svn: 151722
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This function does more or less the same as
MI::readsWritesVirtualRegister(), but it supports bundles as well.
It also determines if any constraint requires reading and writing
operands to use the same register. Most clients want to know.
Use the more modern MO.readsReg() instead of trying to sort out undefs
and partial redefines. Stop supporting the extra full <imp-def> operand
as an alternative to <def,undef> sub-register defines.
llvm-svn: 151690
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Extract a base class and provide four specific sub-classes for iterating
over const/non-const bundles/instructions.
This eliminates the mystery bool constructor argument.
llvm-svn: 151684
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methods are no longer needed now that LinearScan has gone away.
(Contains tweaks trivialSpillEverywhere to enable the removal of getNewVRegs).
llvm-svn: 151658
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direct call.
llvm-svn: 151645
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llvm-svn: 151644
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To avoid problems with zero shifts when getting the bits that move between words
we use a trick: first shift the by amount-1, then do another shift by one. When
amount is 0 (and size 32) we first shift by 31, then by one, instead of by 32.
Also fix a latent bug that emitted the low and high words in the wrong order
when shifting right.
Fixes PR12113.
llvm-svn: 151637
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prediction. ...", it is breaking the Clang build during the Compiler-RT part.
llvm-svn: 151630
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llvm-svn: 151627
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When the GEP index is a vector of pointers, the code that calculated the size
of the element started from the vector type, and not the contained pointer type.
As a result, instead of looking at the data element pointed by the vector, this
code used the size of the vector. This works for 32bit members (on 32bit
systems), but not for other types. Added code to peel the vector type and
added a test.
llvm-svn: 151626
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the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.
Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.
rdar://8979299
llvm-svn: 151623
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Don't attempt to extend physreg live ranges across calls.
<rdar://problem/10942095>
llvm-svn: 151610
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llvm-svn: 151607
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llvm-svn: 151599
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%S5<def> = COPY %S0<kill>
First clear def map of Q1, etc.
No small test case available.
llvm-svn: 151574
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After the SlotIndex slot names were updated, it is possible to apply
stricter checks to live intervals.
Also treat bundles as bags of operands when checking live intervals.
llvm-svn: 151531
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uses of the vreg, since the old kills may no longer be valid. This was causing
-verify-machineinstrs to complain about uses after kills, and could potentially
have been causing subtle register allocation issues, but I haven't come across a
test case yet.
llvm-svn: 151425
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llvm-svn: 151417
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llvm-svn: 151396
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This will limit all register classes to N registers in order to stress
test register allocation.
llvm-svn: 151379
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This is necessary to support the existing ppc lowering code for indirect calls.
Fixes PR12071.
llvm-svn: 151373
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surrounding it.
llvm-svn: 151364
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llvm-svn: 151355
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llvm-svn: 151348
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duplicate patterns for selecting the intrinsics
llvm-svn: 151342
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variable declaration as an argument because we want that address
anyhow for our debug information.
This seems to fix rdar://9965111, at least we have more debug
information than before and from reading the assembly it appears
to be the correct location.
llvm-svn: 151335
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llvm-svn: 151334
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asm.
<rdar://problem/10106006>
llvm-svn: 151303
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llvm-svn: 151274
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