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* Add support for matching mem operands. This fixes PR1133, patch byChris Lattner2008-02-211-1/+7
| | | | | | Eli Friedman. This implements CodeGen/Generic/2008-02-20-MatchingMem.ll. llvm-svn: 47428
* Fix a (harmless) but where vregs were added to the used reg lists for Chris Lattner2008-02-211-9/+26
| | | | | | | | | | inline asms. Fix PR2078 by marking aliases of registers used when a register is marked used. This prevents EAX from being allocated when AX is listed in the clobber set for the asm. llvm-svn: 47426
* Clean up some spilling code using MachineRegisterInfo.Evan Cheng2008-02-211-22/+51
| | | | llvm-svn: 47416
* Remove one of the fixmes that I put in there. From Evan:Bill Wendling2008-02-201-2/+3
| | | | | | | | No need to go up more levels. A def of a register also sets its sub-registers (so if PhysRegInfo[SuperReg] is NULL, it means SuperReg's super registers are not previously defined). llvm-svn: 47399
* Improve some comments explaining the "handle kills" stuff better.Bill Wendling2008-02-201-2/+4
| | | | llvm-svn: 47395
* Fix comment.Bill Wendling2008-02-201-2/+1
| | | | llvm-svn: 47389
* assert is more effective reminder then FIXME tag for unimplemented features.Devang Patel2008-02-201-1/+1
| | | | llvm-svn: 47388
* LegalizeTypes support for scalarizing a vector storeDuncan Sands2008-02-204-8/+46
| | | | | | | | | and splitting extract_subvector. This fixes nine "make check" testcases, for example 2008-02-04-ExtractSubvector.ll and (partially) CodeGen/Generic/vector.ll. llvm-svn: 47384
* Convert Legalize to use the APInt form of ComputeMaskedBits.Dan Gohman2008-02-202-14/+19
| | | | llvm-svn: 47383
* Add explicit keywords.Dan Gohman2008-02-201-1/+1
| | | | llvm-svn: 47382
* Convert DAGCombiner to use the APInt form of ComputeMaskedBits.Dan Gohman2008-02-201-12/+13
| | | | llvm-svn: 47381
* Use APInt::intersects.Dan Gohman2008-02-201-4/+4
| | | | llvm-svn: 47380
* Fix newly-introduced 4.3 warningsAnton Korobeynikov2008-02-202-3/+6
| | | | llvm-svn: 47375
* Update gcc 4.3 warnings fix patch with recent head changesAnton Korobeynikov2008-02-209-26/+44
| | | | llvm-svn: 47368
* Unbreak build with gcc 4.3: provide missed includes and silence most ↵Anton Korobeynikov2008-02-201-0/+1
| | | | | | annoying warnings. llvm-svn: 47367
* Added some comments and reformatted others. No functionality change.Bill Wendling2008-02-201-28/+43
| | | | | | | Added two "FIXMEs" for code that looks dubious to me (but I could be wrong). llvm-svn: 47366
* More constification of things. More comments added. No functionalityBill Wendling2008-02-201-44/+76
| | | | | | changes. (Sorry for any formatting changes that creeped in.) llvm-svn: 47362
* Fix an incredibly subtle bug exposed by Ted's change to APInt profiling.Chris Lattner2008-02-201-1/+1
| | | | | | | | AddNodeIDNode does profiling for a ConstantSDNode, but so does SelectionDAG::getConstant. This profiling should be moved to a common static function in ConstantSDNode. llvm-svn: 47359
* No functionality change:Bill Wendling2008-02-201-31/+42
| | | | | | | - Constified some MachineOperand values. - Added/Modified some comments. llvm-svn: 47358
* Add GetResultInst. First step for multiple return value support.Devang Patel2008-02-191-0/+4
| | | | llvm-svn: 47348
* PR1909: Tail merging pass ran wild. It makes no sense to merge blocks in ↵Evan Cheng2008-02-191-3/+12
| | | | | | order to save a single instruction since a branch will be inserted for each BB. llvm-svn: 47301
* - When DAG combiner is folding a bit convert into a BUILD_VECTOR, it should ↵Evan Cheng2008-02-182-5/+29
| | | | | | | | check if it's essentially a SCALAR_TO_VECTOR. Avoid turning (v8i16) <10, u, u, u> to <10, 0, u, u, u, u, u, u>. Instead, simply convert it to a SCALAR_TO_VECTOR of the proper type. - X86 now normalize SCALAR_TO_VECTOR to (BIT_CONVERT (v4i32 SCALAR_TO_VECTOR)). Get rid of X86ISD::S2VEC. llvm-svn: 47290
* - Remove the previous check which broke coalescer-commute3.llEvan Cheng2008-02-181-5/+5
| | | | | | - For now, conservatively ignore copy MI whose source is a physical register. Commuting its def MI can cause a physical register live interval to be live through a loop (since we know it's live coming into the def MI). llvm-svn: 47281
* New helper function getMBBFromIndex() that given an index in any instruction ↵Roman Levenstein2008-02-181-16/+0
| | | | | | of an MBB returns a pointer the MBB. Reviewed by Evan. llvm-svn: 47267
* For now, avoid commuting def MI for copy MI's whose source is not killed. ↵Evan Cheng2008-02-181-0/+7
| | | | | | That simply trade a live interval for another and because only the non-two-address operands can be folded into loads, may end up pessimising code. llvm-svn: 47262
* I cannot find a libgcc function for this builtin. Therefor expanding it to ↵Andrew Lenharth2008-02-161-5/+15
| | | | | | a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support. llvm-svn: 47213
* Teach LegalizeTypes how to expand the operands ofDuncan Sands2008-02-162-4/+25
| | | | | | br_cc. This fixes 5 "make check" failures. llvm-svn: 47212
* Refactor some code; check if commuteInstruction is able to commute the ↵Evan Cheng2008-02-162-17/+34
| | | | | | instruction. llvm-svn: 47208
* llvm.memory.barrier, and impl for x86 and alphaAndrew Lenharth2008-02-163-0/+20
| | | | llvm-svn: 47204
* Fix typos.Bill Wendling2008-02-161-2/+2
| | | | llvm-svn: 47200
* Rename CountMemOperands to ComputeMemOperandsEnd to reflect whatDan Gohman2008-02-161-12/+9
| | | | | | | it actually does. Simplify CountOperands a little by reusing ComputeMemOperandsEnd. And reword some comments for both. llvm-svn: 47198
* Revert 47177, which was incorrect.Dan Gohman2008-02-161-1/+1
| | | | llvm-svn: 47196
* Make tblgen a little smarter about constants smaller than i32. Currently,Scott Michel2008-02-151-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | tblgen will complain if a sign-extended constant does not fit into a data type smaller than i32, e.g., i16. This causes a problem when certain hex constants are used, such as 0xff for byte masks or immediate xor values. tblgen will try the sign-extended value first and, if the sign extended value would overflow, it tries to see if the unsigned value will fit. Consequently, a software developer can now safely incant: (XORHIr16 R16C:$rA, 0xffff) which is somewhat clearer and more informative than incanting: (XORHIr16 R16C:$rA, (i16 -1)) even if the two are bitwise equivalent. Tblgen also outputs the 64-bit unsigned constant in the generated ISel code when getTargetConstant() is invoked. llvm-svn: 47188
* The copy instruction being coalesced will be removed, it is not a kill.Evan Cheng2008-02-151-2/+2
| | | | llvm-svn: 47179
* Skip over the defs and start at the uses when looking for operandsDan Gohman2008-02-151-1/+1
| | | | | | with the TIED_TO attribute. llvm-svn: 47177
* Use the TargetInstrDescr to determine the number of operandsDan Gohman2008-02-151-3/+3
| | | | | | | that should be checked for the TIED_TO attribute instead of using CountOperands. llvm-svn: 47176
* Teach LegalizeTypes how to promote the flagsDuncan Sands2008-02-152-7/+34
| | | | | | | | | in a ret node. These are created as i32 constants but on some platforms i32 is not legal. This fixes 26 "make check" failures, for example Alpha/2005-07-12-TwoMallocCalls.ll. llvm-svn: 47172
* - Removing the infamous r2rMap_ and rep() method. Now the coalescer will updateEvan Cheng2008-02-154-390/+298
| | | | | | | register defs and uses after each successful coalescing. - Also removed a number of hacks and fixed some subtle kill information bugs. llvm-svn: 47167
* Added CommuteChangesDestination(). This returns true if commuting the specifiedEvan Cheng2008-02-151-1/+21
| | | | | | machine instr will change its definition register. llvm-svn: 47166
* Remove unnecessary #include.Evan Cheng2008-02-151-1/+0
| | | | llvm-svn: 47164
* Use StoreSDNode::getValue instead of calling getOperand directlyDan Gohman2008-02-151-4/+4
| | | | | | with a hard-coded operand number. llvm-svn: 47163
* Fix a miscompilation from Dan's recent apintification.Chris Lattner2008-02-141-3/+1
| | | | llvm-svn: 47128
* In TargetLowering::LowerCallTo, don't assert thatDuncan Sands2008-02-143-16/+25
| | | | | | | | | | | | | | | | | the return value is zero-extended if it isn't sign-extended. It may also be any-extended. Also, if a floating point value was returned in a larger floating point type, pass 1 as the second operand to FP_ROUND, which tells it that all the precision is in the original type. I think this is right but I could be wrong. Finally, when doing libcalls, set isZExt on a parameter if it is "unsigned". Currently isSExt is set when signed, and nothing is set otherwise. This should be right for all calls to standard library routines. llvm-svn: 47122
* Change how FP immediates are handled. Nate Begeman2008-02-143-17/+28
| | | | | | | | | | | | | | 1) ConstantFP is now expand by default 2) ConstantFP is not turned into TargetConstantFP during Legalize if it is legal. This allows ConstantFP to be handled like Constant, allowing for targets that can encode FP immediates as MachineOperands. As a bonus, fix up Itanium FP constants, which now correctly match, and match more constants! Hooray. llvm-svn: 47121
* Support a new type of MachineOperand, MO_FPImmediate, used for holdingNate Begeman2008-02-141-0/+10
| | | | | | FP Immediates, crazily enough llvm-svn: 47117
* Allow the APInt form of ComputeMaskedBits to operate on i128 types.Dan Gohman2008-02-131-4/+7
| | | | llvm-svn: 47101
* Avoid setting bits that aren't demanded.Dan Gohman2008-02-131-3/+3
| | | | llvm-svn: 47098
* Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBitsDan Gohman2008-02-132-44/+52
| | | | | | to pass the mask APInt by value, not by reference. llvm-svn: 47096
* Enable exception handling int JITNicolas Geoffray2008-02-133-2/+31
| | | | llvm-svn: 47079
* Teach LegalizeTypes how to expand and promote CTLZ,Duncan Sands2008-02-133-18/+108
| | | | | | | | | | | | | | | | | | CTTZ and CTPOP. The expansion code differs from that in LegalizeDAG in that it chooses to take the CTLZ/CTTZ count from the Hi/Lo part depending on whether the Hi/Lo value is zero, not on whether CTLZ/CTTZ of Hi/Lo returned 32 (or whatever the width of the type is) for it. I made this change because the optimizers may well know that Hi/Lo is zero and exploit it. The promotion code for CTTZ also differs from that in LegalizeDAG: it uses an "or" to get the right result when the original value is zero, rather than using a compare and select. This also means the value doesn't need to be zero extended. llvm-svn: 47075
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