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* Fix for PR1279. Dead def has a live interval of length 1. Copy coalescing shouldEvan Cheng2007-03-281-3/+5
| | | | | | not violate that. llvm-svn: 35396
* Remove dead codeAnton Korobeynikov2007-03-271-82/+46
| | | | llvm-svn: 35380
* Split big monster into small helpers. No functionality change.Anton Korobeynikov2007-03-271-190/+285
| | | | llvm-svn: 35379
* SDISel does not preserve all, it changes CFG and other info.Evan Cheng2007-03-271-1/+0
| | | | llvm-svn: 35376
* Don't call getOperandConstraint() if operand index is greater thanEvan Cheng2007-03-271-1/+2
| | | | | | TID->numOperands. llvm-svn: 35375
* Fix for PR1266. Don't mark a two address operand IsKill.Evan Cheng2007-03-262-22/+33
| | | | llvm-svn: 35365
* Change findRegisterUseOperand() to return operand index instead.Evan Cheng2007-03-261-4/+4
| | | | llvm-svn: 35363
* Fix reversed logic in getRegsUsed. Rename RegStates to RegsAvailable toDale Johannesen2007-03-261-15/+15
| | | | | | hopefully forestall similar errors. llvm-svn: 35362
* SIGN_EXTEND_INREG requires one extra operand, a ValueType node.Evan Cheng2007-03-261-2/+6
| | | | llvm-svn: 35350
* First step of switch lowering refactoring: perform worklist-drivenAnton Korobeynikov2007-03-251-176/+249
| | | | | | strategy, emit JT's where possible. llvm-svn: 35338
* Implement support for vector operands to inline asm, implementingChris Lattner2007-03-251-4/+16
| | | | | | CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll llvm-svn: 35332
* implement initial support for the silly X constraint. Testcase here: ↵Chris Lattner2007-03-251-0/+2
| | | | | | CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll llvm-svn: 35327
* Implement CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.llChris Lattner2007-03-251-1/+4
| | | | llvm-svn: 35324
* switch TargetLowering::getConstraintType to take the entire constraint,Chris Lattner2007-03-252-24/+28
| | | | | | not just the first letter. No functionality change. llvm-svn: 35322
* don't rely on ADLChris Lattner2007-03-241-1/+1
| | | | llvm-svn: 35299
* Adjust offset to compensate for big endian machines.Evan Cheng2007-03-241-7/+5
| | | | llvm-svn: 35293
* Make sure SEXTLOAD of the specific type is supported on the target.Evan Cheng2007-03-231-0/+4
| | | | llvm-svn: 35289
* Also replace uses of SRL if that's also folded during ReduceLoadWidth().Evan Cheng2007-03-231-1/+8
| | | | llvm-svn: 35286
* A couple of bug fixes for reducing load width xform:Evan Cheng2007-03-231-7/+16
| | | | | | | 1. Address offset is in bytes. 2. Make sure truncate node uses are replaced with new load. llvm-svn: 35274
* Change uses of Function::front to Function::getEntryBlock for readability.Dan Gohman2007-03-221-1/+1
| | | | llvm-svn: 35265
* More opportunities to reduce load size.Evan Cheng2007-03-221-45/+101
| | | | llvm-svn: 35254
* Fix for PR1257. Bug in live range shortening as a result of copy coalescingEvan Cheng2007-03-221-11/+9
| | | | | | where the destination is dead. llvm-svn: 35252
* repair x86 performance, dejagnu problems from previous changeDale Johannesen2007-03-211-2/+2
| | | | llvm-svn: 35245
* fold (truncate (srl (load x), c)) -> (smaller load (x+c/vt bits))Evan Cheng2007-03-211-6/+24
| | | | llvm-svn: 35239
* Potential spiller improvement.Evan Cheng2007-03-201-0/+27
| | | | llvm-svn: 35228
* do not share old induction variables when this would result in invalidDale Johannesen2007-03-201-0/+16
| | | | | | instructions (that would have to be split later) llvm-svn: 35227
* maintain LiveIn when splitting blocks (register scavenging needs it)Dale Johannesen2007-03-202-1/+29
| | | | llvm-svn: 35226
* Fix some VC++ warnings.Jeff Cohen2007-03-201-0/+1
| | | | llvm-svn: 35224
* Code clean up.Lauro Ramos Venancio2007-03-201-23/+20
| | | | llvm-svn: 35220
* Minor bug.Evan Cheng2007-03-201-1/+2
| | | | llvm-svn: 35219
* CopyToReg source operand can be a physical register.Lauro Ramos Venancio2007-03-201-3/+19
| | | | llvm-svn: 35213
* First cut trivial re-materialization support.Evan Cheng2007-03-204-26/+151
| | | | llvm-svn: 35208
* Remove -reduce-joining-phys-regs options. Make it on by default.Evan Cheng2007-03-191-3/+1
| | | | llvm-svn: 35165
* Minor bug fix.Evan Cheng2007-03-191-1/+1
| | | | llvm-svn: 35153
* - Merge UsedBlocks info after two virtual registers are coalesced.Evan Cheng2007-03-181-23/+30
| | | | | | - Use distance to closest use to determine whether to abort coalescing. llvm-svn: 35141
* Keep UsedBlocks info accurate.Evan Cheng2007-03-182-0/+6
| | | | llvm-svn: 35140
* Track the BB's where each virtual register is used.Evan Cheng2007-03-171-15/+22
| | | | llvm-svn: 35135
* Joining a live interval of a physical register with a virtual one can turn outEvan Cheng2007-03-171-0/+54
| | | | | | | | | | | | to be really bad. Once they are joined they are not broken apart. Also, physical intervals cannot be spilled! Added a heuristic as a workaround for this. Be careful coalescing with a physical register if the virtual register uses are "far". Check if there are uses in the same loop as the source (copy instruction). Check if it is in the loop preheader, etc. llvm-svn: 35134
* Use SmallSet instead of std::set.Evan Cheng2007-03-171-1/+1
| | | | llvm-svn: 35133
* If sdisel has decided to sink GEP index expression into any BB. Replace all usesEvan Cheng2007-03-171-22/+37
| | | | | | in that BB. llvm-svn: 35132
* Turn on GEP index sinking by default.Evan Cheng2007-03-161-7/+0
| | | | llvm-svn: 35127
* Stupid bug.Evan Cheng2007-03-161-1/+1
| | | | llvm-svn: 35126
* Sink a binary expression into its use blocks if it is a loop invariantEvan Cheng2007-03-161-0/+92
| | | | | | | computation used as GEP indexes and if the expression can be folded into target addressing mode of GEP load / store use types. llvm-svn: 35123
* Added isLegalAddressExpression hook to test if the given expression can beEvan Cheng2007-03-161-0/+8
| | | | | | folded into target addressing mode for the given type. llvm-svn: 35121
* Debugging output stuff.Evan Cheng2007-03-151-4/+4
| | | | llvm-svn: 35117
* Estimate a cost using the possible number of scratch registers required and useEvan Cheng2007-03-141-9/+47
| | | | | | | | | | it as a late BURR scheduling tie-breaker. Intuitively, it's good to push down instructions whose results are liveout so their long live ranges won't conflict with other values which are needed inside the BB. Further prioritize liveout instructions by the number of operands which are calculated within the BB. llvm-svn: 35109
* Try schedule def + use closer whne Sethi-Ullman numbers are the same.Evan Cheng2007-03-131-6/+38
| | | | | | | | | | | | | | | | | | | | | e.g. t1 = op t2, c1 t3 = op t4, c2 and the following instructions are both ready. t2 = op c3 t4 = op c4 Then schedule t2 = op first. i.e. t4 = op c4 t2 = op c3 t1 = op t2, c1 t3 = op t4, c2 This creates more short live intervals which work better with the register allocator. llvm-svn: 35089
* More flexible TargetLowering LSR hooks for testing whether an immediate is a ↵Evan Cheng2007-03-121-3/+13
| | | | | | legal target address immediate or scale. llvm-svn: 35076
* If a virtual register is already marked alive in this block, that means it isEvan Cheng2007-03-091-1/+6
| | | | | | alive in one of the successor block. Do not add it to the kill list. llvm-svn: 35041
* Print preds / succs BB numbers.Evan Cheng2007-03-091-2/+2
| | | | llvm-svn: 35040
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