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* [CodeGenPrepare] Fix r265264 (again).Peter Zotov2016-04-031-3/+3
| | | | | | | Don't require TLI for SinkCmpExpression, like it wasn't before r265264. llvm-svn: 265271
* [CodeGenPrepare] Fix r265264.Peter Zotov2016-04-031-3/+3
| | | | | | | The case where there was no TargetLowering was not handled, leading to null pointer dereferences. llvm-svn: 265265
* [CodeGenPrepare] Avoid sinking soft-FP comparisonsPeter Zotov2016-04-031-5/+9
| | | | | | | | | | | | | | | Sinking comparisons in CGP can undo the job of hoisting them done earlier by LICM, and soft-FP makes this an expensive mistake. A common pattern that produces floating point comparisons uniform over a loop is an explicit check for division by zero. If the divisor is hoisted out of the loop, the comparison can also be, but hoisting the function that unwinds is never legal, since it may cause side effects in the loop body prior to the unwinding to not be executed. Differential Revision: http://reviews.llvm.org/D18744 llvm-svn: 265264
* Swift Calling Convention: add swifterror attribute.Manman Ren2016-04-013-0/+9
| | | | | | | | | | | | A ``swifterror`` attribute can be applied to a function parameter or an AllocaInst. This commit does not include any target-specific change. The target-specific optimization will come as a follow-up patch. Differential Revision: http://reviews.llvm.org/D18092 llvm-svn: 265189
* Don't use an i64 return type with webkit_jsccSanjoy Das2016-04-011-6/+7
| | | | | | | | | Re-enable an assertion enabled by Justin Lebar in rL265092. rL265092 was breaking test/CodeGen/X86/deopt-intrinsic.ll because webkit_jscc does not like non-i64 return types. Change the test case to not do that. llvm-svn: 265099
* Fix Sub-register Rewriting in Aggressive Anti-Dependence BreakerChuang-Yu Cheng2016-04-011-13/+16
| | | | | | | | | | | | | | | | | | | Previously, HandleLastUse would delete RegRef information for sub-registers if they were dead even if their corresponding super-register were still live. If the super-register were later renamed, then the definitions of the sub-register would not be updated appropriately. This patch alters the behavior so that RegInfo information for sub-registers is only deleted when the sub-register and super-register are both dead. This resolves PR26775. This is the mirror image of Hal's r227311 commit. Author: Tom Jablin (tjablin) Reviewers: kbarton uweigand nemanjai hfinkel http://reviews.llvm.org/D18448 llvm-svn: 265097
* Revert "Protect some assertions with NDEBUG rather than DEBUG()."Justin Lebar2016-04-011-7/+6
| | | | | | This reverts r265092, because it breaks CodeGen/X86/deopt-intrinsic.ll. llvm-svn: 265093
* Protect some assertions with NDEBUG rather than DEBUG().Justin Lebar2016-04-011-6/+7
| | | | | | | DEBUG() only runs if you pass -debug, but these assertions are generally useful. llvm-svn: 265092
* [ifcnv] Add brief comment explaining what ifcnv is.Justin Lebar2016-04-011-1/+2
| | | | llvm-svn: 265088
* Move the DebugEmissionKind enum from DIBuilder into DICompileUnit.Adrian Prantl2016-03-312-3/+2
| | | | | | | | | | | | | This mostly cosmetic patch moves the DebugEmissionKind enum from DIBuilder into DICompileUnit. DIBuilder is not the right place for this enum to live in — a metadata consumer should not have to include DIBuilder.h. I also added a Verifier check that checks that the emission kind of a DICompileUnit is actually legal. http://reviews.llvm.org/D18612 <rdar://problem/25427165> llvm-svn: 265077
* [AsmPrinter] Print aliases in topological orderTim Shen2016-03-311-1/+18
| | | | | | | | | | Print aliases in topological order, that is, for any alias a = b, b must be printed before a. This is because on some targets (e.g. PowerPC) linker expects aliases in such an order to generate correct TOC information. GCC also prints aliases in topological order. llvm-svn: 265064
* Fix PR26940 where compiles times regressed massively.Chandler Carruth2016-03-311-33/+30
| | | | | | | | | | | | | | | Patch by Jonas Paulsson. Original description: Bugfix in buildSchedGraph() to make -dag-maps-huge-region work properly I found that the reduction of the maps did in fact never happen in this test case. This was because *all* the stores / loads were made with addresses from arguments and they thus became "unknown" stores / loads. Fixed by removing continue statements and making sure that the test for reduction always takes place. Differential Revision: http://reviews.llvm.org/D18673 llvm-svn: 265063
* fix typo; NFCSanjay Patel2016-03-311-2/+1
| | | | llvm-svn: 265054
* Change eliminateCallFramePseudoInstr() to return an iteratorHans Wennborg2016-03-311-9/+1
| | | | | | | | | | | | | | | | | | | | | This will become necessary in a subsequent change to make this method merge adjacent stack adjustments, i.e. it might erase the previous and/or next instruction. It also greatly simplifies the calls to this function from Prolog- EpilogInserter. Previously, that had a bunch of logic to resume iteration after the call; now it just continues with the returned iterator. Note that this changes the behaviour of PEI a little. Previously, it attempted to re-visit the new instruction created by eliminateCallFramePseudoInstr(). That code was added in r36625, but I can't see any reason for it: the new instructions will obviously not be pseudo instructions, they will not have FrameIndex operands, and we have already accounted for the stack adjustment. Differential Revision: http://reviews.llvm.org/D18627 llvm-svn: 265036
* Don't use potentially invalidated iteratorStephan Bergmann2016-03-311-2/+4
| | | | | | | | | | | | If the lhs is evaluated before the rhs, FuncletI's operator-> can trigger the assert(isHandleInSync() && "invalid iterator access!"); at include/llvm/ADT/DenseMap.h:1061. (Happens e.g. when compiled with GCC 6.) Differential Revision: http://reviews.llvm.org/D18440 llvm-svn: 265024
* Prevent X86ISelLowering from merging volatile loadsNirav Dave2016-03-312-14/+9
| | | | | | | | | | | | | Change isConsecutiveLoads to check that loads are non-volatile as this is a requirement for any load merges. Propagate change to two callers. Reviewers: RKSimon Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D18546 llvm-svn: 265013
* CodeGen: Factor out code for tail call result compatibility check; NFCMatthias Braun2016-03-301-0/+36
| | | | llvm-svn: 264959
* LegalizeDAG: Don't replace vector store with integer if not legalMatt Arsenault2016-03-303-41/+87
| | | | | | | | | | | For the same reason as the corresponding load change. Note that ExpandStore is completely broken for non-byte sized element vector stores, but preserve the current broken behavior which has tests for it. The behavior should be the same, but now introduces a new typed store that is incorrectly split later rather than doing it directly. llvm-svn: 264928
* LegalizeDAG: Don't replace vector load with integer unless legalMatt Arsenault2016-03-303-28/+71
| | | | | | | | | | | | | On AMDGPU we want to be able to promote i64/f64 loads to v2i32. If the access is unaligned, this would conclude that since i64 is legal, it would convert it back to i64 and there is an endless legalization loop. Extract the logic for scalarizing the load into a new TargetLowering function, where this can also replace the custom function AMDGPU has for this. llvm-svn: 264927
* MachineSink: make shouldSink a TII target hookFiona Glaser2016-03-291-7/+2
| | | | | | | Some targets may disagree on what they want sunk or not sunk, so make this a target hook instead of hardcoded. llvm-svn: 264799
* Add a print method to MachineFunctionProperties for better error messagesDerek Schuff2016-03-292-2/+37
| | | | | | | | | This makes check failures much easier to understand. Make it empty (but leave it in the class) for NDEBUG builds. Differential Revision: http://reviews.llvm.org/D18529 llvm-svn: 264780
* MachineVerifier: On dead-def live segments, check that corresponding machine ↵Matthias Braun2016-03-291-3/+18
| | | | | | operand has a dead flag llvm-svn: 264769
* LiveVariables: Fix typo and shorten commentMatthias Braun2016-03-291-4/+2
| | | | llvm-svn: 264768
* Add support for no-jump-tablesNirav Dave2016-03-291-2/+7
| | | | | | | | | | | | | Add function soft attribute to the generation of Jump Tables in CodeGen as initial step towards clang support of gcc's no-jump-table support Reviewers: hans, echristo Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D18321 llvm-svn: 264756
* Add MachineVerifier check for AllVRegsAllocated MachineFunctionPropertyDerek Schuff2016-03-295-15/+20
| | | | | | | | | | | | | | | | | Summary: Check that any function that has the property set is free of virtual register operands. Also, it is actually VirtRegMap (and not the register allocators) that acutally remove the VReg operands (except for RegAllocFast). Reviewers: qcolombet Subscribers: MatzeB, llvm-commits, qcolombet Differential Revision: http://reviews.llvm.org/D18535 llvm-svn: 264755
* Swift Calling Convention: add swiftself attribute.Manman Ren2016-03-293-0/+9
| | | | | | Differential Revision: http://reviews.llvm.org/D17866 llvm-svn: 264754
* RegisterPressure: Simplify liveness tracking when lanemasks are not checked.Matthias Braun2016-03-291-31/+66
| | | | | | | | | | | | | | Split RegisterOperands code that collects defs/uses into a variant with and without lanemask tracking. This is a bit of code duplication, but there are enough subtle differences between the two variants that this seems cleaner (and potentially faster). This also fixes a problem where lanes where tracked even though TrackLaneMasks was false. This is part of the fix for http://llvm.org/PR27106. I will commit the testcase when it is completely fixed. llvm-svn: 264696
* LiveVariables: Do not remove dead flags from vreg operandsMatthias Braun2016-03-291-3/+8
| | | | | | | Also add a FIXME comment on why Mips RDDSP causes bogus dead flags to be added which LiveVariables cleans up by accident. llvm-svn: 264695
* [Codegen] Decrease minimum jump table density.Kyle Butt2016-03-292-8/+23
| | | | | | | | | | | Minimum density for both optsize and non optsize are now options -sparse-jump-table-density (default 10) for non optsize functions -dense-jump-table-density (default 40) for optsize functions, which matches the current default. This improves several benchmarks at google at the cost of a small codesize increase. For code compiled with -Os, the old behavior continues llvm-svn: 264689
* MIRParser: Add %subreg.xxx syntax for subregister index operandsMatthias Braun2016-03-283-1/+27
| | | | | | Differential Revision: http://reviews.llvm.org/D18279 llvm-svn: 264608
* Introduce MachineFunctionProperties and the AllVRegsAllocated propertyDerek Schuff2016-03-2814-1/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | MachineFunctionProperties represents a set of properties that a MachineFunction can have at particular points in time. Existing examples of this idea are MachineRegisterInfo::isSSA() and MachineRegisterInfo::tracksLiveness() which will eventually be switched to use this mechanism. This change introduces the AllVRegsAllocated property; i.e. the property that all virtual registers have been allocated and there are no VReg operands left. With this mechanism, passes can declare that they require a particular property to be set, or that they set or clear properties by implementing e.g. MachineFunctionPass::getRequiredProperties(). The MachineFunctionPass base class verifies that the requirements are met, and handles the setting and clearing based on the delcarations. Passes can also directly query and update the current properties of the MF if they want to have conditional behavior. This change annotates the target-independent post-regalloc passes; future changes will also annotate target-specific ones. Reviewers: qcolombet, hfinkel Differential Revision: http://reviews.llvm.org/D18421 llvm-svn: 264593
* NFC: skip FenceInst up-front in AtomicExpandPass.James Y Knight2016-03-281-5/+5
| | | | llvm-svn: 264583
* Revert "NFC: static_assert instead of comment"JF Bastien2016-03-261-3/+1
| | | | | | | | | | | This reverts commit fa36fcff16c7d4f78204d6296bf96c3558a4a672. Causes the following Windows failure: C:\Buildbot\Slave\llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast\llvm.src\lib\CodeGen\MachineInstr.cpp(762): error C2338: must be trivially copyable to memmove llvm-svn: 264516
* NFC: static_assert instead of commentJF Bastien2016-03-261-1/+3
| | | | | | | | | | Summary: isPodLike is as close as we have for is_trivially_copyable. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D18483 llvm-svn: 264515
* Minor code cleanup. NFC.Junmo Park2016-03-261-1/+1
| | | | llvm-svn: 264505
* [MachineCopyPropagation] Expose more dead copies across instructions with ↵Jun Bum Lim2016-03-251-3/+14
| | | | | | | | | | | regmasks When encountering instructions with regmasks, instead of cleaning up all the elements in MaybeDeadCopies map, remove only the instructions erased. By keeping more instruction in MaybeDeadCopies, this change will expose more dead copies across instructions with regmasks. llvm-svn: 264462
* Prevent construction of cycle in DAG store mergeNirav Dave2016-03-253-40/+44
| | | | | | | | | | | | | | | | | | | | | When merging stores in DAGCombiner, add check to ensure that no dependenices exist that would cause the construction of a cycle in our DAG. This may happen if one store has a data dependence on another instruction (e.g. a load) which itself has a (chain) dependence on another store being merged. These stores cannot be merged safely and doing so results in a cycle that is discovered in LegalizeDAG. This test is only done in cases where Antialias analysis is used (UseAA) as non-AA store merge candidates will be merged logically after all loads which have been checked to not alias. Reviewers: ahatanak, spatel, niravd, arsenm, hfinkel, tstellarAMD, jyknight Subscribers: llvm-commits, tberghammer, danalbert, srhines Differential Revision: http://reviews.llvm.org/D18336 llvm-svn: 264461
* CodeGen: Don't iterate over operands after we've erased an MIJustin Bogner2016-03-251-13/+20
| | | | | | | | | | | This fixes a use-after-free introduced 3 years ago, in r182872 ;) The code more or less worked because the memory that CopyMI was pointing to happened to still be valid, but lots of tests would crash if you ran under ASAN with the recycling allocator changes from llvm.org/PR26808 llvm-svn: 264455
* CodeGen: Fix a use-after-free in TIIJustin Bogner2016-03-251-2/+4
| | | | | | Found by ASAN with the recycling allocator changes from PR26808. llvm-svn: 264443
* Consider regmasks when computing register-based DBG_VALUE live rangesReid Kleckner2016-03-252-33/+63
| | | | | | | | | | | | | | Now register parameters that aren't saved to the stack or CSRs are considered dead after the first call. Previously the debugger would show whatever was in the register. Fixes PR26589 Reviewers: aprantl Differential Revision: http://reviews.llvm.org/D17211 llvm-svn: 264429
* CXX TLS: collect return blocks after SelectAllBasicBlocks.Manman Ren2016-03-241-7/+15
| | | | | | | | | | It is incorrect to get the corresponding MBB for a ReturnInst before SelectAllBasicBlocks since SelectAllBasicBlocks can change the correspondence between a ReturnInst and the MBB it is in. PR27062 llvm-svn: 264358
* Reduce code duplication by extracting out a helper function; NFCSanjoy Das2016-03-242-30/+21
| | | | llvm-svn: 264355
* Lower varargs correctly in deopt bundle loweringSanjoy Das2016-03-241-0/+1
| | | | | | | Earlier we were ignoring varargs in LowerCallSiteWithDeoptBundle because populateCallLoweringInfo does not set CallLoweringInfo::IsVarArg. llvm-svn: 264354
* LiveInterval: Fix Distribute() failing on liveranges with unused VNInfosMatthias Braun2016-03-241-8/+13
| | | | | | This fixes http://llvm.org/PR26991 llvm-svn: 264345
* Revert "Recommitted r263424 "Supporting all entities declared in lexical ↵Reid Kleckner2016-03-246-211/+51
| | | | | | | | | | | scope in LLVM debug info." After fixing PR26942 (the fix is included in this commit)." This reverts commit r264280. This broke building Chromium for iOS. We'll upload a reproducer to the PR soon. llvm-svn: 264334
* Add lowering support for llvm.experimental.deoptimizeSanjoy Das2016-03-244-0/+42
| | | | | | | | | | | | | | | Summary: Only adds support for "naked" calls to llvm.experimental.deoptimize. Support for round-tripping through RewriteStatepointsForGC will come as a separate patch (should be simpler than this one). Reviewers: reames Subscribers: sanjoy, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D18429 llvm-svn: 264329
* [Statepoints] Fix yet another issue around gc pointer uniqueingSanjoy Das2016-03-242-19/+22
| | | | | | | | | | | | | Given that StatepointLowering now uniques derived pointers before putting them in the per-statepoint spill map, we may end up with missing entries for derived pointers when we visit a gc.relocate on a pointer that was de-duplicated away. Fix this by keeping two maps, one mapping gc pointers to their de-duplicated values, and one mapping a de-duplicated value to the slot it is spilled in. llvm-svn: 264320
* Minor cosmestic changes (NFC)Sanjoy Das2016-03-241-7/+7
| | | | | | | - Reflow comments - Rename function llvm-svn: 264319
* [debuginfo] Include dwo_name in the split unit to improve dwp diagnosticsDavid Blaikie2016-03-241-1/+4
| | | | | | | | | | | | | | | | | | | When multiple DWP files are merged together and duplicate DWO IDs are found it's currently difficult to give an actionable error message - the DW_AT_name of the CU could be provided, but might be identical (if the same source file is built into two different configurations), which doesn't help the user identify the problem. When no intermediate DWP files are generated, the path to the two DWO files could be provided - but is lost once the DWOs are merged into a DWP. So, include the name of the DWO (dwo_name) in the split file so that collissions involving a source CU from a DWP can be better diagnosed. (improvements to llvm-dwp using this to come shortly) llvm-svn: 264316
* CodeGen: extend RHS when splitting ATOMIC_CMP_SWAP_WITH_SUCCESS.Tim Northover2016-03-241-3/+18
| | | | | | | | | | | | | If the operation's type has been promoted during type legalization, we need to account for the fact that the high bits of the comparison operand are likely unspecified. The LHS is usually zero-extended, but MIPS sign extends it, so we have to be slightly careful. Patch by Simon Dardis. llvm-svn: 264296
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