summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
Commit message (Collapse)AuthorAgeFilesLines
* Fix potential crash if DAGCombine on stores sees a half typePete Cooper2012-06-211-1/+2
| | | | llvm-svn: 158927
* The inline asm operand modifier 'c' is suppose Jack Carter2012-06-211-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | to be generic across architectures. It has the following description in the gnu sources: Substitute immediate value without immediate syntax Several Architectures such as x86 have local implementations of operand modifier 'c' which go beyond the above description slightly. To make use of the generic modifiers without overriding local implementation one can make a call to the base class method for AsmPrinter::PrintAsmOperand() in the locally derived method's "default" case in the switch statement. That way if it is already defined locally the generic version will never get called. This change is needed when test/CodeGen/generic/asm-large-immediate.ll failed on a native Mips board. The test was assuming a generic implementation was in place. Affected files: lib/Target/Mips/MipsAsmPrinter.cpp: Changed the default case to call the base method. lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Added 'c' to the switch cases. test/CodeGen/Mips/asm-large-immediate.ll Mips compiled version of the generic one Contributer: Jack Carter llvm-svn: 158925
* Emit a single _udivmodsi4 libcall instead of two separate _udivsi3 andEvan Cheng2012-06-211-5/+7
| | | | | | | | _umodsi3 libcalls if they have the same arguments. This optimization was apparently broken if one of the node was replaced in place. rdar://11714607 llvm-svn: 158900
* Update regunits in RegisterCoalescer::reMaterializeTrivialDef.Jakob Stoklund Olesen2012-06-211-6/+4
| | | | | | Old code would only update physreg live intervals. llvm-svn: 158881
* Remove spurious typedefs.Jakob Stoklund Olesen2012-06-201-3/+0
| | | | llvm-svn: 158878
* Remove the RenderMachineFunction HTML output pass.Jakob Stoklund Olesen2012-06-206-1374/+0
| | | | | | | I don't think anyone has been using this functionality for a while, and it is getting in the way of refactoring now. llvm-svn: 158876
* Remove the -live-regunits command line option.Jakob Stoklund Olesen2012-06-201-12/+4
| | | | | | Register allocators depend on it being permanently enabled now. llvm-svn: 158873
* Fix some more LiveInterval enumerations.Jakob Stoklund Olesen2012-06-202-13/+12
| | | | | | Deterministically enumerate the virtual registers instead. llvm-svn: 158872
* Remove LiveIntervalUnions from RegAllocBase.Jakob Stoklund Olesen2012-06-204-167/+14
| | | | | | They are living in LiveRegMatrix now. llvm-svn: 158868
* Convert RAGreedy to LiveRegMatrix interference checking.Jakob Stoklund Olesen2012-06-204-92/+169
| | | | | | | | | | | | | | | | | Stop depending on the LiveIntervalUnions in RegAllocBase, they are about to be removed. The changes are mostly replacing register alias iterators with regunit iterators, and querying LiveRegMatrix instrad of RegAllocBase. InterferenceCache is converted to work with per-regunit LiveIntervalUnions, and it checks fixed regunit interference separately, using the fixed live intervals provided by LiveIntervalAnalysis. The local splitting helper calcGapWeights() is also considering fixed regunit interference which is kept on the side now. llvm-svn: 158867
* Convert RABasic to using LiveRegMatrix interference checking.Jakob Stoklund Olesen2012-06-203-69/+67
| | | | | | | Stop using the LiveIntervalUnions provided by RegAllocBase, they will be removed soon. llvm-svn: 158866
* Enable register unit liveness by default.Jakob Stoklund Olesen2012-06-201-1/+1
| | | | | | Soon we won't need to compute live intervals for physical registers. llvm-svn: 158865
* Teach PBQPBuilder::build() about regunit interference.Jakob Stoklund Olesen2012-06-201-33/+31
| | | | | | | Filter out physreg candidates with regunit interferrence. Also compute regmask interference more efficiently. llvm-svn: 158864
* Avoid iterating with LiveIntervals::iterator.Jakob Stoklund Olesen2012-06-203-41/+45
| | | | | | | | | | That is a DenseMap iterator keyed by pointers, so the iteration order is nondeterministic. I would like to replace the DenseMap with an IndexedMap which doesn't allow iteration. llvm-svn: 158856
* Add users of a MERGE_VALUE node to the worklist to process again when the ↵Pete Cooper2012-06-201-0/+3
| | | | | | node is removed. Sorry, no test case. Foudn it by inspection of the code llvm-svn: 158839
* Only update regunit live ranges that have been precomputed.Jakob Stoklund Olesen2012-06-201-4/+8
| | | | | | | | | | | Regunit live ranges are computed on demand, so when mi-sched calls handleMove, some regunits may not have live ranges yet. That makes updating them easier: Just skip the non-existing ranges. They will be computed correctly from the rescheduled machine code when they are needed. llvm-svn: 158831
* Delete dead code.Jakob Stoklund Olesen2012-06-201-48/+0
| | | | llvm-svn: 158827
* Fix DAGCombine to deal with ext-conversion of pre/post_inc loads.Hal Finkel2012-06-201-1/+8
| | | | | | The test case for this will come with the PPC indexed preinc loads commit. llvm-svn: 158822
* Fixing a compiler warning in MSVC 10.Aaron Ballman2012-06-201-1/+1
| | | | llvm-svn: 158820
* Fix two rather subtle internal vs. external linker issues.Chandler Carruth2012-06-201-25/+20
| | | | | | | | | | | | | | | | | | | | | | I'll admit I'm not entirely satisfied with this change, but it seemed the cleanest option. Other suggestions quite welcome The issue is that the traits specializations have static methods which return the typedef'ed PHI_iterator type. In both the IR and MI layers this is typedef'ed to a custom iterator class defined in an anonymous namespace giving the types and the functions returning them internal linkage. However, because the traits specialization is defined in the 'llvm' namespace (where it has to be, specialized template lives there), and is in turn used in the templated implementation of the SSAUpdater. This led to the linkage conflict that Clang now warns about. The simplest solution to me was just to define the PHI_iterator as a nested class inside the trait specialization. That way it still doesn't get scoped widely, it can't be accidentally reused somewhere, etc. This is a little gross just because nested class definitions are a little gross, but the alternatives seem more ad-hoc. llvm-svn: 158799
* A new algorithm for computing LoopInfo. Temporarily disabled.Andrew Trick2012-06-201-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | -stable-loops enables a new algorithm for generating the Loop forest. It differs from the original algorithm in a few respects: - Not determined by use-list order. - Initially guarantees RPO order of block and subloops. - Linear in the number of CFG edges. - Nonrecursive. I didn't want to change the LoopInfo API yet, so the block lists are still inclusive. This seems strange to me, and it means that building LoopInfo is not strictly linear, but it may not be a problem in practice. At least the block lists start out in RPO order now. In the future we may add an attribute or wrapper analysis that allows other passes to assume RPO order. The primary motivation of this work was not to optimize LoopInfo, but to allow reproducing performance issues by decomposing the compilation stages. I'm often unable to do this with the current LoopInfo, because the loop tree order determines Loop pass order. Serializing the IR tends to invert the order, which reverses the optimization order. This makes it nearly impossible to debug interdependent loop optimizations such as LSR. I also believe this will provide more stable performance results across time. llvm-svn: 158790
* Move the implementation of LoopInfo into LoopInfoImpl.h.Andrew Trick2012-06-201-9/+5
| | | | | | | | | The implementation only needs inclusion from LoopInfo.cpp and MachineLoopInfo.cpp. Clients of the interface should only include the interface. This makes the interface readable and speeds up rebuilds after modifying the implementation. llvm-svn: 158787
* Add regunit liveness support to LiveIntervals::handleMove().Jakob Stoklund Olesen2012-06-191-43/+50
| | | | | | | When LiveIntervals is tracking fixed interference in regunits, make sure to update those intervals as well. Currently guarded by -live-regunits. llvm-svn: 158766
* Tidy up.Chad Rosier2012-06-191-17/+20
| | | | llvm-svn: 158762
* Add an ensureMaxAlignment() function to MachineFrameInfo (analogous toChad Rosier2012-06-192-3/+2
| | | | | | | | | ensureAlignment() in MachineFunction). Also, drop setMaxAlignment() in favor of this new function. This creates a main entry point to setting MaxAlignment, which will be helpful for future work. No functionality change intended. llvm-svn: 158758
* Add DAG-combines for aggressive FMA formation.Lang Hames2012-06-191-0/+43
| | | | | | | | | | | | | | | | | | | | This patch adds DAG combines to form FMAs from pairs of FADD + FMUL or FSUB + FMUL. The combines are performed when: (a) Either AllowExcessFPPrecision option (-enable-excess-fp-precision for llc) OR UnsafeFPMath option (-enable-unsafe-fp-math) are set, and (b) TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) is true for the type of the FADD/FSUB, and (c) The FMUL only has one user (the FADD/FSUB). If your target has fast FMA instructions you can make use of these combines by overriding TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) to return true for types supported by your FMA instruction, and adding patterns to match ISD::FMA to your FMA instructions. llvm-svn: 158757
* 80 col.Jakob Stoklund Olesen2012-06-191-7/+13
| | | | llvm-svn: 158755
* Implement PPCInstrInfo::isCoalescableExtInstr().Jakob Stoklund Olesen2012-06-191-3/+19
| | | | | | | | | | | | | The PPC::EXTSW instruction preserves the low 32 bits of its input, just like some of the x86 instructions. Use it to reduce register pressure when the low 32 bits have multiple uses. This requires a small change to PeepholeOptimizer since EXTSW takes a 64-bit input register. This is related to PR5997. llvm-svn: 158743
* Style: Don't reuse variables for multiple purposes.Jakob Stoklund Olesen2012-06-191-8/+7
| | | | | | No functional change. llvm-svn: 158742
* Move the support for using .init_array from ARM to the genericRafael Espindola2012-06-191-8/+40
| | | | | | | | | | TargetLoweringObjectFileELF. Use this to support it on X86. Unlike ARM, on X86 it is not easy to find out if .init_array should be used or not, so the decision is made via TargetOptions and defaults to off. Add a command line option to llc that enables it. llvm-svn: 158692
* Allow up to 64 functional units per processor itinerary.Hal Finkel2012-06-182-7/+7
| | | | | | | This patch changes the type used to hold the FU bitset from unsigned to uint64_t. This will be needed for some upcoming PowerPC itineraries. llvm-svn: 158679
* Guard private fields that are unused in Release builds with #ifndef NDEBUG.Benjamin Kramer2012-06-162-1/+9
| | | | llvm-svn: 158608
* Remove final verification in RABasic.Jakob Stoklund Olesen2012-06-151-20/+0
| | | | | | | We now have a proper machine code verifier pass between register allocation and rewriting. llvm-svn: 158577
* Print out register number in InlineSpiller.Jakob Stoklund Olesen2012-06-151-2/+2
| | | | llvm-svn: 158575
* Accept null PhysReg arguments to checkRegMaskInterference.Jakob Stoklund Olesen2012-06-152-2/+3
| | | | | | | Calling checkRegMaskInterference(VirtReg) checks if VirtReg crosses any regmask operands, regardless of the registers they clobber. llvm-svn: 158563
* Remove assignments which aren't used afterwards.Bill Wendling2012-06-151-3/+1
| | | | llvm-svn: 158535
* Use regunit liveness in RegisterCoalescer when it is available.Jakob Stoklund Olesen2012-06-151-13/+21
| | | | | | | We only do very limited physreg coalescing now, but we still merge virtual registers into reserved registers. llvm-svn: 158526
* Make machine verifier check the first instruction of the last bundle instead ofAkira Hatanaka2012-06-141-8/+8
| | | | | | the last instruction of a basic block. llvm-svn: 158468
* Make comment slightly more helpful.Lang Hames2012-06-141-1/+1
| | | | llvm-svn: 158467
* misched: disable SSA check pending PR13112.Andrew Trick2012-06-141-2/+4
| | | | llvm-svn: 158461
* sched: fix latency of memory dependence chain edges for consistency.Andrew Trick2012-06-131-13/+21
| | | | | | | | | | | For store->load dependencies that may alias, we should always use TrueMemOrderLatency, which may eventually become a subtarget hook. In effect, we should guarantee at least TrueMemOrderLatency on at least one DAG path from a store to a may-alias load. This should fix the standard mode as well as -enable-aa-sched-mi". llvm-svn: 158380
* sched: Avoid trivially redundant DAG edges. Take the one with higher latency.Andrew Trick2012-06-131-3/+20
| | | | llvm-svn: 158379
* misched: When querying RegisterPressureTracker, always save current and max ↵Andrew Trick2012-06-111-2/+8
| | | | | | pressure. llvm-svn: 158340
* misched: regpressure getMaxPressureDelta, revert accidental checkin.Andrew Trick2012-06-111-8/+2
| | | | llvm-svn: 158339
* Allocate the contents of DwarfDebug's StringMaps in a single big ↵Benjamin Kramer2012-06-092-5/+6
| | | | | | BumpPtrAllocator. llvm-svn: 158265
* Register pressure: added getPressureAfterInstr.Andrew Trick2012-06-091-33/+80
| | | | llvm-svn: 158256
* Sketch a LiveRegMatrix analysis pass.Jakob Stoklund Olesen2012-06-093-0/+296
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The LiveRegMatrix represents the live range of assigned virtual registers in a Live interval union per register unit. This is not fundamentally different from the interference tracking in RegAllocBase that both RABasic and RAGreedy use. The important differences are: - LiveRegMatrix tracks interference per register unit instead of per physical register. This makes interference checks cheaper and assignments slightly more expensive. For example, the ARM D7 reigster has 24 aliases, so we would check 24 physregs before assigning to one. With unit-based interference, we check 2 units before assigning to 2 units. - LiveRegMatrix caches regmask interference checks. That is currently duplicated functionality in RABasic and RAGreedy. - LiveRegMatrix is a pass which makes it possible to insert target-dependent passes between register allocation and rewriting. Such passes could tweak the register assignments with interference checking support from LiveRegMatrix. Eventually, RABasic and RAGreedy will be switched to LiveRegMatrix. llvm-svn: 158255
* Also compute MBB live-in lists in the new rewriter pass.Jakob Stoklund Olesen2012-06-096-89/+32
| | | | | | | | | This deduplicates some code from the optimizing register allocators, and it means that it is now possible to change the register allocators' solutions simply by editing the VirtRegMap between the register allocator pass and the rewriter. llvm-svn: 158249
* Reintroduce VirtRegRewriter.Jakob Stoklund Olesen2012-06-087-78/+121
| | | | | | | | | | | | | | | | | | OK, not really. We don't want to reintroduce the old rewriter hacks. This patch extracts virtual register rewriting as a separate pass that runs after the register allocator. This is possible now that CodeGen/Passes.cpp can configure the full optimizing register allocator pipeline. The rewriter pass uses register assignments in VirtRegMap to rewrite virtual registers to physical registers, and it inserts kill flags based on live intervals. These finalization steps are the same for the optimizing register allocators: RABasic, RAGreedy, and PBQP. llvm-svn: 158244
* Start implementing pre-ra if-converter: using speculation and selects to ↵Evan Cheng2012-06-081-6/+15
| | | | | | eliminate branches. llvm-svn: 158234
OpenPOWER on IntegriCloud