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* Use the attribute enums to query if a parameter has an attribute.Bill Wendling2012-10-091-6/+6
| | | | llvm-svn: 165550
* Add in the first step of the multiple pointer support. This adds in support ↵Micah Villmow2012-10-091-6/+7
| | | | | | | | to the data layout for specifying a per address space pointer size. The next step is to update the optimizers to allow them to optimize the different address spaces with this information. llvm-svn: 165505
* Create enums for the different attributes.Bill Wendling2012-10-0911-33/+42
| | | | | | | We use the enums to query whether an Attributes object has that attribute. The opaque layer is responsible for knowing where that specific attribute is stored. llvm-svn: 165488
* Fix up comment to be more clear.Eric Christopher2012-10-081-2/+2
| | | | llvm-svn: 165463
* Refactor the AddrMode class out of TLI to its own header file.Nadav Rotem2012-10-081-1/+1
| | | | | | | | This class is used by LSR and a number of places in the codegen. This is the first step in de-coupling LSR from TLI, and creating a new interface in between them. llvm-svn: 165455
* Don't crash on extra evil irreducible control flow.Jakob Stoklund Olesen2012-10-082-2/+10
| | | | | | | | | | | | | | When the CFG contains a loop with multiple entry blocks, the traces computed by MachineTraceMetrics don't always have the same nice properties. Loop back-edges are normally excluded from traces, but MachineLoopInfo doesn't recognize loops with multiple entry blocks, so those back-edges may be included. Avoid asserting when that happens by adding an isEarlierInSameTrace() function that accurately determines if a dominating block is part of the same trace AND is above the currrent block in the trace. llvm-svn: 165434
* Fixup comment.Eric Christopher2012-10-081-1/+1
| | | | llvm-svn: 165427
* Fixup comments.Eric Christopher2012-10-081-2/+2
| | | | llvm-svn: 165426
* misched: remove the unused getSpecialAddressLatency hook.Andrew Trick2012-10-081-40/+7
| | | | llvm-svn: 165418
* misched: remove forceUnitLatencies. Defaults are handled by the default ↵Andrew Trick2012-10-082-35/+30
| | | | | | SchedModel llvm-svn: 165417
* misched: avoid scheduling an instruction twice.Andrew Trick2012-10-081-25/+29
| | | | llvm-svn: 165416
* Move TargetData to DataLayout.Micah Villmow2012-10-0835-147/+147
| | | | llvm-svn: 165402
* Remove unused MachineInstr constructors that don't take a DebugLoc argument.Craig Topper2012-10-071-29/+0
| | | | llvm-svn: 165382
* Fix indentation. Remove 'else' after return. No functional change.Craig Topper2012-10-071-11/+8
| | | | llvm-svn: 165381
* Remove unused but set variable flagged by GCC.Benjamin Kramer2012-10-051-4/+0
| | | | llvm-svn: 165331
* Simplify code, don't or a bool with an uint64_t.Benjamin Kramer2012-10-051-2/+2
| | | | | | No functionality change. llvm-svn: 165321
* When merging connsecutive stores, use vectors to store the constant zero.Nadav Rotem2012-10-041-34/+57
| | | | llvm-svn: 165267
* Update this a bit more to represent how the prologue should work:Eric Christopher2012-10-041-3/+4
| | | | | | | | | | a) frame setup instructions define the prologue b) we shouldn't change our location mid-stream Add a test to make sure that the stack adjustment stays within the prologue. llvm-svn: 165250
* Get MCSchedModel directly from the subtarget.Jakob Stoklund Olesen2012-10-041-2/+3
| | | | | | | Not all targets have itineraries, but the subtarget always has an MCSchedModel. llvm-svn: 165236
* Switch MachineTraceMetrics to the new TargetSchedModel interface.Jakob Stoklund Olesen2012-10-042-32/+27
| | | | llvm-svn: 165235
* Fix reg mask slot test, and preserve LiveIntervals and VirtRegMap in the PBQPLang Hames2012-10-041-1/+3
| | | | | | allocator. Fixes PR13945. llvm-svn: 165201
* Enable -schedmodel, but prefer itineraries until we have more benchmark data.Andrew Trick2012-10-041-52/+51
| | | | llvm-svn: 165188
* Update to use the predicate methods to query if an attribute exists.Bill Wendling2012-10-031-17/+17
| | | | llvm-svn: 165163
* Fix a cycle in the DAG. In this code we replace multiple loads with a single ↵Nadav Rotem2012-10-031-7/+19
| | | | | | | | | | | load and multiple stores with a single load. We create the wide loads and stores (and their chains) before we remove the scalar loads and stores and fix the DAG chain. We attempted to merge loads with a different chain. When that happened, the assumption that it is safe to RAUW broke and a cycle was introduced. llvm-svn: 165148
* A DAGCombine optimization for mergeing consecutive stores to memory. The ↵Nadav Rotem2012-10-031-0/+395
| | | | | | | | | | | | | | | | | | | | | optimization is not profitable in many cases because modern processors perform multiple stores in parallel and merging stores prior to merging requires extra work. We handle two main cases: 1. Store of multiple consecutive constants: q->a = 3; q->4 = 5; In this case we store a single legal wide integer. 2. Store of multiple consecutive loads: int a = p->a; int b = p->b; q->a = a; q->b = b; In this case we load/store either ilegal vector registers or legal wide integer registers. llvm-svn: 165125
* Fixed a bug in the ExecutionDependencyFix pass that caused dependencies to ↵Silviu Baranga2012-10-031-3/+6
| | | | | | not propagate through implicit defs. llvm-svn: 165102
* Revert 165051-165049 while looking into the foreach.m failure inEric Christopher2012-10-031-16/+11
| | | | | | more detail. llvm-svn: 165099
* The early if conversion pass is ready to be used as an opt-in.Jakob Stoklund Olesen2012-10-031-3/+3
| | | | | | | | | | | Enable the pass by default for targets that request it, and change the -enable-early-ifcvt to the opposite -disable-early-ifcvt. There are still some x86 regressions when enabling early if-conversion because of the missing machine models. Disable the pass for x86 until machine models are added. llvm-svn: 165075
* Revert "Don't use a debug location for frame setup instructions in the"Eric Christopher2012-10-021-4/+3
| | | | | | | This reverts 165055 and 165052 temporarily while I look at debugger failures. llvm-svn: 165071
* Remove the old coalescer algorithm.Jakob Stoklund Olesen2012-10-021-344/+1
| | | | | | | The new algorithm has been enabled by default for almost a week now and seems to be stable. llvm-svn: 165062
* Handle reserved registers more accurately in handleMove().Jakob Stoklund Olesen2012-10-021-8/+7
| | | | | | | | | | | | Reserved register live ranges look like a set of dead defs - any uses of reserved registers are ignored. Instead of skipping the updating of reserved register operands entirely, just ignore the use operands and treat the def operands normally. No test case, handleMove() is not commonly used yet. llvm-svn: 165060
* Make sure the whole live range is covered when values are pruned twice.Jakob Stoklund Olesen2012-10-021-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | JoinVals::pruneValues() calls LIS->pruneValue() to avoid conflicts when overlapping two different values. This produces a set of live range end points that are used to reconstruct the live range (with SSA update) after joining the two registers. When a value is pruned twice, the set of end points was insufficient: v1 = DEF v1 = REPLACE1 v1 = REPLACE2 KILL v1 The end point at KILL would only reconstruct the live range from REPLACE2 to KILL, leaving the range REPLACE1-REPLACE2 dead. Add REPLACE2 as an end point in this case so the full live range is reconstructed. This fixes PR13999. llvm-svn: 165056
* 80-col.Eric Christopher2012-10-021-2/+2
| | | | llvm-svn: 165054
* Don't use a debug location for frame setup instructions in theEric Christopher2012-10-021-3/+4
| | | | | | | prologue. Also skip frame setup instructions when looking for the first location. llvm-svn: 165052
* Remove the SavePoint infrastructure from fast isel, replaceEric Christopher2012-10-021-11/+16
| | | | | | | with just an insert point from the MachineBasicBlock and let the location be updated as we access it. llvm-svn: 165049
* Fix PR13991: legalizing an overflowing multiplication operation is harder thanDuncan Sands2012-10-021-7/+15
| | | | | | | the add/sub case since in the case of multiplication you also have to check that the operation in the larger type did not overflow. llvm-svn: 165017
* Use dyn_cast instead of isa and cast.Jakub Staszak2012-09-301-10/+8
| | | | | | No functionality change. llvm-svn: 164924
* Revert r164910 because it causes failures to several phase2 builds.Nadav Rotem2012-09-301-254/+0
| | | | llvm-svn: 164911
* A DAGCombine optimization for merging consecutive stores. This optimization ↵Nadav Rotem2012-09-301-0/+254
| | | | | | | | | | | | | | | | | | | is not profitable in many cases because moden processos can store multiple values in parallel, and preparing the consecutive store requires some work. We only handle these cases: 1. Consecutive stores where the values and consecutive loads. For example: int a = p->a; int b = p->b; q->a = a; q->b = b; 2. Consecutive stores where the values are constants. Foe example: q->a = 4; q->b = 5; llvm-svn: 164910
* Speculatively revert commit 164885 (nadav) in the hope of ressurecting a pile ofDuncan Sands2012-09-291-252/+0
| | | | | | | | | | | | | | | | | | | | buildbots. Original commit message: A DAGCombine optimization for merging consecutive stores. This optimization is not profitable in many cases because moden processos can store multiple values in parallel, and preparing the consecutive store requires some work. We only handle these cases: 1. Consecutive stores where the values and consecutive loads. For example: int a = p->a; int b = p->b; q->a = a; q->b = b; 2. Consecutive stores where the values are constants. Foe example: q->a = 4; q->b = 5; llvm-svn: 164890
* Tidy up to match coding standards. Remove 'else' after 'return' and moving ↵Craig Topper2012-09-291-27/+24
| | | | | | operators to end of preceding line. No functional change intended. llvm-svn: 164887
* Replace a couple if/elses around similar calls with conditional operators on ↵Craig Topper2012-09-291-17/+6
| | | | | | the varying arguments. No functional change. llvm-svn: 164886
* A DAGCombine optimization for merging consecutive stores. This optimization ↵Nadav Rotem2012-09-291-0/+252
| | | | | | | | | | | | | | | | | | | is not profitable in many cases because moden processos can store multiple values in parallel, and preparing the consecutive store requires some work. We only handle these cases: 1. Consecutive stores where the values and consecutive loads. For example: int a = p->a; int b = p->b; q->a = a; q->b = b; 2. Consecutive stores where the values are constants. Foe example: q->a = 4; q->b = 5; llvm-svn: 164885
* Remove <def,read-undef> flags from partial redefinitions.Jakob Stoklund Olesen2012-09-271-0/+6
| | | | | | | | | The new coalescer can turn a full virtual register definition into a partial redef by merging another value into an unused vector lane. Make sure to clear the <read-undef> flag on such defs. llvm-svn: 164807
* Enable the new coalescer algorithm by default.Jakob Stoklund Olesen2012-09-271-1/+1
| | | | | | | The new coalescer is better at merging values into unused vector lanes, improving NEON code. llvm-svn: 164794
* Don't dereference begin() on an empty vector.Jakob Stoklund Olesen2012-09-271-1/+1
| | | | | | | | The fix is obvious and the only test case I have is horrible, so I am not including it. The problem shows up when self-hosting clang on i386 with -new-coalescer enabled. llvm-svn: 164793
* Avoid dereferencing a NULL pointer.Jakob Stoklund Olesen2012-09-271-1/+1
| | | | | | Fixes PR13943. llvm-svn: 164778
* Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. ↵Sylvestre Ledru2012-09-274-35/+35
| | | | | | See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 llvm-svn: 164768
* Fix a typo 'iff' => 'if'Sylvestre Ledru2012-09-274-35/+35
| | | | llvm-svn: 164767
* Remove the `hasFnAttr' method from Function.Bill Wendling2012-09-269-15/+15
| | | | | | | The hasFnAttr method has been replaced by querying the Attributes explicitly. No intended functionality change. llvm-svn: 164725
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