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* DAGCombiner: Deduplicate code.Benjamin Kramer2012-01-151-24/+14
| | | | llvm-svn: 148217
* Truncate of undef is just undef of smaller size.Craig Topper2012-01-151-5/+6
| | | | llvm-svn: 148205
* Speculatively revert commit 148175 (rafael), to see if this fixesDuncan Sands2012-01-141-4/+2
| | | | | | | | non-determinism in the 32 bit dragonegg buildbot. Original commit message: Only emit the Leh_func_endN symbol when needed. llvm-svn: 148191
* Only emit the Leh_func_endN symbol when needed.Rafael Espindola2012-01-141-2/+4
| | | | llvm-svn: 148175
* misched: Initial code for building an MI level scheduling DAGAndrew Trick2012-01-144-21/+113
| | | | llvm-svn: 148174
* Move physreg dependency generation into aptly named addPhysRegDeps.Andrew Trick2012-01-142-155/+182
| | | | llvm-svn: 148173
* misched: Added ScheduleDAGInstrs::IsPostRAAndrew Trick2012-01-144-11/+17
| | | | llvm-svn: 148172
* misched: Invoke the DAG builder on each sequence of schedulable instructions.Andrew Trick2012-01-141-6/+31
| | | | llvm-svn: 148171
* Move things around to make the file navigable, even though it will probably ↵Andrew Trick2012-01-141-19/+32
| | | | | | be split up later. llvm-svn: 148170
* After r147827 and r147902, it's now possible for unallocatable registers to beEvan Cheng2012-01-141-6/+22
| | | | | | | | | | | | | | | | | | | live across BBs before register allocation. This miscompiled 197.parser when a cmp + b are optimized to a cbnz instruction even though the CPSR def is live-in a successor. cbnz r6, LBB89_12 ... LBB89_12: ble LBB89_1 The fix consists of two parts. 1) Teach LiveVariables that some unallocatable registers might be liveouts so don't mark their last use as kill if they are. 2) ARM constantpool island pass shouldn't form cbz / cbnz if the conditional branch does not kill CPSR. rdar://10676853 llvm-svn: 148168
* Remove previous commit while I debug the bot failures.Rafael Espindola2012-01-131-0/+3
| | | | llvm-svn: 148156
* Remove label that is not used anymore.Rafael Espindola2012-01-131-3/+0
| | | | llvm-svn: 148150
* Remove pointless mode line in .cpp file.Andrew Trick2012-01-131-1/+1
| | | | llvm-svn: 148143
* Added the MachineSchedulerPass skeleton.Andrew Trick2012-01-135-0/+241
| | | | llvm-svn: 148105
* wrong filenameAndrew Trick2012-01-131-1/+1
| | | | llvm-svn: 148103
* 80-col violationAndrew Trick2012-01-131-3/+3
| | | | llvm-svn: 148102
* DAGCombine's logic for forming pre- and post- indexed loads / stores were beingEvan Cheng2012-01-131-9/+44
| | | | | | | | | | | | | | | | overly conservative. It was concerned about cases where it would prohibit folding simple [r, c] addressing modes. e.g. ldr r0, [r2] ldr r1, [r2, #4] => ldr r0, [r2], #4 ldr r1, [r2] Change the logic to look for such cases which allows it to form indexed memory ops more aggressively. rdar://10674430 llvm-svn: 148086
* Revert accidental commit.Bill Wendling2012-01-121-65/+0
| | | | llvm-svn: 148065
* Fix the code that was WRONG.Bill Wendling2012-01-121-0/+65
| | | | | | | The registers are placed into the saved registers list in the reverse order, which is why the original loop was written to loop backwards. llvm-svn: 148064
* Added FPOW, FEXP, FLOG to PromoteNode so that custom actions can be set to ↵Pete Cooper2012-01-121-0/+18
| | | | | | | | Promote for those operations. Sorry, no test case yet llvm-svn: 148050
* When hoisting common code, watch out for uses which are marked "kill". If theEvan Cheng2012-01-121-0/+5
| | | | | | | | | | | killed registers are needed below the insertion point, then unset the kill marker. Sorry I'm not able to find a reduced test case. rdar://10660944 llvm-svn: 148043
* Allow targets to select source order pre-RA scheduler.Evan Cheng2012-01-121-1/+2
| | | | llvm-svn: 148033
* Make SplitAnalysis::UseSlots private.Jakob Stoklund Olesen2012-01-122-6/+10
| | | | llvm-svn: 148031
* Make data structures private.Jakob Stoklund Olesen2012-01-113-11/+17
| | | | llvm-svn: 147979
* Sink spillInterferences into RABasic.Jakob Stoklund Olesen2012-01-113-63/+62
| | | | | | This helper method is too simplistic for RAGreedy. llvm-svn: 147976
* Cleanup.Jakob Stoklund Olesen2012-01-111-9/+0
| | | | llvm-svn: 147975
* Move RegAllocBase into its own cpp file separate from RABasic.Jakob Stoklund Olesen2012-01-113-312/+336
| | | | | | No functional change. llvm-svn: 147972
* On AVX, we can load v8i32 at a time. The bug happens when two uneven loads ↵Nadav Rotem2012-01-111-5/+23
| | | | | | | | | | are used. When we load the v12i32 type, the GenWidenVectorLoads method generates two loads: v8i32 and v4i32 and attempts to use CONCAT_VECTORS to join them. In this fix I concat undef values to widen the smaller value. The test "widen_load-2.ll" also exposes this bug on AVX. llvm-svn: 147964
* Teach the X86 instruction selection to do some heroic transforms toChandler Carruth2012-01-111-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | detect a pattern which can be implemented with a small 'shl' embedded in the addressing mode scale. This happens in real code as follows: unsigned x = my_accelerator_table[input >> 11]; Here we have some lookup table that we look into using the high bits of 'input'. Each entity in the table is 4-bytes, which means this implicitly gets turned into (once lowered out of a GEP): *(unsigned*)((char*)my_accelerator_table + ((input >> 11) << 2)); The shift right followed by a shift left is canonicalized to a smaller shift right and masking off the low bits. That hides the shift right which x86 has an addressing mode designed to support. We now detect masks of this form, and produce the longer shift right followed by the proper addressing mode. In addition to saving a (rather large) instruction, this also reduces stalls in Intel chips on benchmarks I've measured. In order for all of this to work, one part of the DAG needs to be canonicalized *still further* than it currently is. This involves removing pointless 'trunc' nodes between a zextload and a zext. Without that, we end up generating spurious masks and hiding the pattern. llvm-svn: 147936
* Detect when a value is undefined on an edge to a landing pad.Jakob Stoklund Olesen2012-01-111-4/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Consider this code: int h() { int x; try { x = f(); g(); } catch (...) { return x+1; } return x; } The variable x is undefined on the first edge to the landing pad, but it has the f() return value on the second edge to the landing pad. SplitAnalysis::getLastSplitPoint() would assume that the return value from f() was live into the landing pad when f() throws, which is of course impossible. Detect these cases, and treat them as if the landing pad wasn't there. This allows spill code to be inserted after the function call to f(). <rdar://problem/10664933> llvm-svn: 147912
* Exclusively use SplitAnalysis::getLastSplitPoint().Jakob Stoklund Olesen2012-01-113-25/+14
| | | | | | | | | Delete the alternative implementation in LiveIntervalAnalysis. These functions computed the same thing, but SplitAnalysis caches the result. llvm-svn: 147911
* Avoid CSE of instructions which define physical registers across MBBs unlessEvan Cheng2012-01-111-4/+12
| | | | | | the physical registers are not allocatable. llvm-svn: 147902
* 80 col violation.Evan Cheng2012-01-101-2/+2
| | | | llvm-svn: 147884
* Add 'llvm_unreachable' to passify GCC's understanding of the constraintsChandler Carruth2012-01-105-0/+5
| | | | | | | | of several newly un-defaulted switches. This also helps optimizers (including LLVM's) recognize that every case is covered, and we should assume as much. llvm-svn: 147861
* Remove unnecessary default cases in switches that cover all enum values.David Blaikie2012-01-1010-24/+0
| | | | llvm-svn: 147855
* Fix a bug in the legalization of shuffle vectors. When we emulate shuffles ↵Nadav Rotem2012-01-101-1/+3
| | | | | | using BUILD_VECTORS we may be using a BV of different type. Make sure to cast it back. llvm-svn: 147851
* Allow machine-cse to look across MBB boundary when cse'ing instructions thatEvan Cheng2012-01-101-15/+54
| | | | | | | | | | define physical registers. It's currently very restrictive, only catching cases where the CE is in an immediate (and only) predecessor. But it catches a surprising large number of cases. rdar://10660865 llvm-svn: 147827
* Remove the logging streamer.Rafael Espindola2012-01-101-5/+0
| | | | llvm-svn: 147820
* Avoid eraseing copies from a reserved register unless the definition can beEvan Cheng2012-01-081-0/+26
| | | | | | safely proven not to have been clobbered. No small test case possible. llvm-svn: 147751
* Replace some uses of hasNUsesOfValue(0, X) with !hasAnyUseOfValue(X)Craig Topper2012-01-071-4/+4
| | | | llvm-svn: 147733
* Add some DAG combines for SUBC/SUBE. If nothing uses the carry/borrow out of ↵Craig Topper2012-01-071-2/+51
| | | | | | subc, turn it into a sub. Turn (subc x, x) into 0 with no borrow. Turn (subc x, 0) into x with no borrow. Turn (subc -1, x) into (xor x, -1) with no borrow. Turn sube with no borrow in into subc. llvm-svn: 147728
* Optimize reserved register coalescing.Jakob Stoklund Olesen2012-01-071-0/+25
| | | | | | | | | | | | | | | | | Reserved registers don't have proper live ranges, their LiveInterval simply has a snippet of liveness for each def. Virtual registers with a single value that is a copy of a reserved register (typically %esp) can be coalesced with the reserved register if the live range doesn't overlap any reserved register defs. When coalescing with a reserved register, don't modify the reserved register live range. Just leave it as a bunch of dead defs. This eliminates quadratic coalescer behavior in i386 functions with many function calls. PR11699 llvm-svn: 147726
* Use the 'regalloc' debug tag for most register allocator tracing.Jakob Stoklund Olesen2012-01-073-3/+3
| | | | llvm-svn: 147725
* Revert part of r147716. Looks like x87 instructions kill markers are all messedEvan Cheng2012-01-071-9/+11
| | | | | | | | | | up so branch folding pass can't use the scavenger. :-( This doesn't breaks anything currently. It just means targets which do not carefully update kill markers cannot run post-ra scheduler (not new, it has always been the case). We should fix this at some point since it's really hacky. llvm-svn: 147719
* Added a late machine instruction copy propagation pass. This catchesEvan Cheng2012-01-079-38/+274
| | | | | | | | | | | | | | | | | | | | | | | | opportunities that only present themselves after late optimizations such as tail duplication .e.g. ## BB#1: movl %eax, %ecx movl %ecx, %eax ret The register allocator also leaves some of them around (due to false dep between copies from phi-elimination, etc.) This required some changes in codegen passes. Post-ra scheduler and the pseudo-instruction expansion passes have been moved after branch folding and tail merging. They were before branch folding before because it did not always update block livein's. That's fixed now. The pass change makes independently since we want to properly schedule instructions after branch folding / tail duplication. rdar://10428165 rdar://10640363 llvm-svn: 147716
* Missing raw_ostream.h breaks MSVC build.Andrew Trick2012-01-071-0/+1
| | | | llvm-svn: 147703
* Add comment.Chad Rosier2012-01-061-0/+4
| | | | llvm-svn: 147696
* Add a comment and ensure that anyone else looking at this code doesn't startEric Christopher2012-01-061-6/+5
| | | | | | to bleed from the eyes. llvm-svn: 147695
* Use const vector references instead of a vector copy. Spotted by Devang.Eric Christopher2012-01-061-4/+4
| | | | llvm-svn: 147694
* Use -> instead of (*iter).Eric Christopher2012-01-061-10/+10
| | | | llvm-svn: 147693
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