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llvm-svn: 91475
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llvm-svn: 91440
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isPodLike type trait. This is a generally useful type trait for
more than just DenseMap, and we really care about whether something
acts like a pod, not whether it really is a pod.
llvm-svn: 91421
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1. Only perform (zext (shl (zext x), y)) -> (shl (zext x), y) when y is a constant. This makes sure it remove at least one zest.
2. If the shift is a left shift, make sure the original shift cannot shift out bits.
llvm-svn: 91399
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stuff isn't used just yet.
We want to model the GCC `-fno-schedule-insns' and `-fno-schedule-insns2'
flags. The hypothesis is that the people who use these flags know what they are
doing, and have hand-optimized the C code to reduce latencies and other
conflicts.
The idea behind our scheme to turn off scheduling is to create a map "on the
side" during DAG generation. It will order the nodes by how they appeared in the
code. This map is then used during scheduling to get the ordering.
llvm-svn: 91392
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the only use of its source.
llvm-svn: 91390
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llvm-svn: 91380
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llvm-svn: 91378
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$ svn merge -c -91161 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r91161 into '.':
U lib/CodeGen/BranchFolding.cpp
U lib/CodeGen/MachineBasicBlock.cpp
$ svn merge -c -91113 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r91113 into '.':
G lib/CodeGen/MachineBasicBlock.cpp
$ svn merge -c -91101 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r91101 into '.':
U include/llvm/CodeGen/MachineBasicBlock.h
G lib/CodeGen/MachineBasicBlock.cpp
$ svn merge -c -91092 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r91092 into '.':
G include/llvm/CodeGen/MachineBasicBlock.h
G lib/CodeGen/MachineBasicBlock.cpp
llvm-svn: 91376
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llvm-svn: 91362
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Bill for spotting this!
llvm-svn: 91355
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but we need it to actually be 4-bytes in the FDE.
llvm-svn: 91337
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llvm-svn: 91278
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llvm-svn: 91275
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llvm-svn: 91274
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own pass: CalculateSpillWeights.
llvm-svn: 91273
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results.
llvm-svn: 91233
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a vector type.
llvm-svn: 91181
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branches only to a landing pad. Without this check, the compiler would go into
an infinite loop because the branch to a landing pad is an "abnormal" edge which
wasn't being taken into account.
This is the meat of that fix:
if (!PrevBB.canFallThrough() && !MBB->BranchesToLandingPad(MBB)) {
The other stuff is simplification of the "branches to a landing pad" code.
llvm-svn: 91161
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llvm-svn: 91159
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llvm-svn: 91158
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aggregate return values. This fixes PR5754.
llvm-svn: 91145
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This is used in some weird cases like general dynamic TLS model.
This fixes PR5723
llvm-svn: 91144
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build bots.
llvm-svn: 91113
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llvm-svn: 91103
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- Loosen the restrictions when checking of it branches to a landing pad.
- Make the loop more efficient by checking the '.insert' return value.
- Do cheaper checks first.
llvm-svn: 91101
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more than one successor. Normally, these extra successors are dead. However,
some of them may branch to exception handling landing pads. If we remove those
successors, then the landing pads could go away if all predecessors to it are
removed. Before, it was checking if the direct successor was the landing
pad. But it could be the result of jumping through multiple basic blocks to get
to it. If we were to only check for the existence of an EH_LABEL in the basic
block and not remove successors if it's in there, then it could stop actually
dead basic blocks from being removed.
llvm-svn: 91092
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do not try to use the variable die.
llvm-svn: 91077
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subregister indices. e.g.:
%reg16404:1<def> = MOV8rr %reg16412:2<kill>
llvm-svn: 91061
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Create global variable DIEs after creating subprogram DIEs. This allows function level static variable's to find their context at the time of DIE creation.
llvm-svn: 91055
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llvm-svn: 91051
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The coalescer is supposed to clean these up, but when setting up parameters
for a function call, there may be copies to physregs. If the defining
instruction has been LICM'ed far away, the coalescer won't touch it.
The register allocation hint does not always work - when the register
allocator is backtracking, it clears the hints.
This patch is more conservative than r90502, and does not break
483.xalancbmk/i686. It still breaks the PowerPC bootstrap, so it is disabled
by default, and can be enabled with the -trivial-coalesce-ends option.
llvm-svn: 91049
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llvm-svn: 90979
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the target.
llvm-svn: 90970
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When a call is placed to spill an interval this spiller will first try to
break the interval up into its component values. Single value intervals and
intervals which have already been split (or are the result of previous splits)
are spilled by the default spiller.
Splitting intervals as described above may improve the performance of generated
code in some circumstances. This work is experimental however, and it still
miscompiles many benchmarks. It's not recommended for general use yet.
llvm-svn: 90951
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isl lowering code.
llvm-svn: 90925
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primary used by selectdag passes.
llvm-svn: 90922
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llvm-svn: 90919
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llvm-svn: 90918
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llvm-svn: 90917
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llvm-svn: 90898
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There is no need to supply ModuleCU to addType() as a parameter.
llvm-svn: 90858
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llvm-svn: 90857
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llvm-svn: 90816
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llvm-svn: 90815
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llvm-svn: 90805
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llvm-svn: 90804
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llvm-svn: 90759
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llvm-svn: 90744
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from i32 to platform's largest native type
llvm-svn: 90741
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