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* [DWARF] Versioning for DWARF constants; verify FORMsPaul Robinson2017-04-201-4/+13
| | | | | | | | | | | | | Associate the version-when-defined with definitions of standard DWARF constants. Identify the "vendor" for DWARF extensions. Use this information to verify FORMs in .debug_abbrev are defined as of the DWARF version specified in the associated unit. Removed two tests that had specified DWARF v1 (which essentially does not exist). Differential Revision: http://reviews.llvm.org/D30785 llvm-svn: 300875
* [Recycler] Add asan/msan annotations.Benjamin Kramer2017-04-201-2/+5
| | | | | | | | | | This enables use after free and uninit memory checking for memory returned by a recycler. SelectionDAG currently relies on the opcode of a free'd node being ISD::DELETED_NODE, so poke a hole in the asan poison for SDNode opcodes. This means that we won't find some issues, but only in SDag. llvm-svn: 300868
* Fix use-after-frees on memory allocated in a Recycler.Benjamin Kramer2017-04-201-1/+5
| | | | | | | | This will become asan errors once the patch lands that poisons the memory after free. The x86 change is a hack, but I don't see how to solve this properly at the moment. llvm-svn: 300867
* CodeGen: Let frame index value type match alloca addr spaceYaxun Liu2017-04-202-7/+7
| | | | | | | | | | | | | | | | | | | | | | Recently alloca address space has been added to data layout. Due to this change, pointer returned by alloca may have different size as pointer in address space 0. However, currently the value type of frame index is assumed to be of the same size as pointer in address space 0. This patch fixes that. Most targets assume alloca returning pointer in address space 0, which is the default alloca address space. Therefore it is NFC for them. AMDGCN target with amdgiz environment requires this change since it assumes alloca returning pointer to addr space 5 and its size is 32, which is different from the size of pointer in addr space 0 which is 64. Differential Revision: https://reviews.llvm.org/D32021 llvm-svn: 300864
* [DAGCombiner] use more local variables in isAlias(); NFCISanjay Patel2017-04-201-9/+11
| | | | llvm-svn: 300860
* [APInt] Rename getSignBit to getSignMaskCraig Topper2017-04-204-33/+33
| | | | | | | | getSignBit is a static function that creates an APInt with only the sign bit set. getSignMask seems like a better name to convey its functionality. In fact several places use it and then store in an APInt named SignMask. Differential Revision: https://reviews.llvm.org/D32108 llvm-svn: 300856
* [DAGCombiner] fix variable names in isAlias(); NFCISanjay Patel2017-04-201-27/+28
| | | | | | | We started with zero-based params and switched to one-based locals... Also, variables start with a capital and functions do not. llvm-svn: 300854
* [DAGCombiner] give names to repeated calcs in isAlias(); NFCISanjay Patel2017-04-201-13/+11
| | | | llvm-svn: 300850
* [globalisel] Enable tracing the legalizer with --debug-only=legalize-mirDaniel Sanders2017-04-202-6/+32
| | | | | | | | | | | | Reviewers: t.p.northover, ab, qcolombet, aditya_nandakumar, rovka, kristof.beyls Reviewed By: kristof.beyls Subscribers: dberris, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D31750 llvm-svn: 300847
* [MVT][SVE] Scalable vector MVTs (3/3)Amara Emerson2017-04-201-2/+2
| | | | | | | | | | | | Adds MVT::ElementCount to represent the length of a vector which may be scalable, then adds helper functions that work with it. Patch by Graham Hunter. Differential Revision: https://reviews.llvm.org/D32019 llvm-svn: 300842
* [MVT][SVE] Scalable vector MVTs (1/3)Amara Emerson2017-04-202-15/+9
| | | | | | | | | | | | | | | | This patch adds a few helper functions to obtain new vector value types based on existing ones without needing to care about whether they are scalable or not. I've confined their use to a few common locations right now, and targets that don't have scalable vectors should never need to care about these. Patch by Graham Hunter. Differential Revision: https://reviews.llvm.org/D32017 llvm-svn: 300838
* [SelectionDAG] Fix another place that was passing a large value to ↵Craig Topper2017-04-201-15/+17
| | | | | | APInt::lshrInPlace. llvm-svn: 300821
* [SelectionDAG] Use getActiveBits() and countTrailingZeros() to avoid ↵Craig Topper2017-04-201-4/+3
| | | | | | creating temporary APInts with lshr and trunc. NFCI llvm-svn: 300819
* Recommit "[APInt] Add back the asserts that check that the APInt shift ↵Craig Topper2017-04-201-2/+3
| | | | | | | | methods aren't called with values larger than BitWidth." This includes a fix to clamp a right shift of larger than BitWidth in DAG combining. llvm-svn: 300816
* Do not run frame verification if target does not use frame instructionsSerge Pavlov2017-04-201-0/+2
| | | | llvm-svn: 300807
* Fix bug that caused DwarfExpression to drop DW_OP_deref from FI locationsAdrian Prantl2017-04-195-19/+27
| | | | | | | | | | | - introduced in r300522 and found via the Swift LLDB testsuite. The fix is to set the location kind to memory whenever an FrameIndex location is emitted. rdar://problem/31707602 llvm-svn: 300793
* Revert "Fix bug that caused DwarfExpression to drop DW_OP_deref from FI ↵Adrian Prantl2017-04-195-27/+19
| | | | | | | | locations" This reverts commit r300790. llvm-svn: 300792
* Fix bug that caused DwarfExpression to drop DW_OP_deref from FI locationsAdrian Prantl2017-04-195-19/+27
| | | | | | | | | | | - introduced in r300522 and found via the Swift LLDB testsuite. The fix is to set the location kind to memory whenever an FrameIndex location is emitted. rdar://problem/31707602 llvm-svn: 300790
* Temporarily revert r299221 to fix nondeterminism in ThinLTO builder.Galina Kistanova2017-04-191-35/+1
| | | | llvm-svn: 300783
* [DAG] add splat vector support for 'or' in SimplifyDemandedBitsSanjay Patel2017-04-191-2/+1
| | | | | | | | | | | I've changed one of the tests to not fold away, but we didn't and still don't do the transform that the comment claims we do (and I don't know why we'd want to do that). Follow-up to: https://reviews.llvm.org/rL300725 https://reviews.llvm.org/rL300763 llvm-svn: 300772
* [DAG] add splat vector support for 'xor' in SimplifyDemandedBitsSanjay Patel2017-04-192-3/+2
| | | | | | | | | This allows forming more 'not' ops, so we get improvements for ISAs that have and-not. Follow-up to: https://reviews.llvm.org/rL300725 llvm-svn: 300763
* [APInt] Cast calls to add/sub/mul overflow methods to void if only their ↵Craig Topper2017-04-191-1/+1
| | | | | | | | | | overflow bool out param is used. This is preparation for a clang change to improve the [[nodiscard]] warning to not be ignored on methods that return a class marked [[nodiscard]] that are defined in the class itself. See D32207. We should consider adding wrapper methods to APInt that return the overflow flag directly and discard the APInt result. This would eliminate the void casts and the need to create a bool before the call to pass to the out param. llvm-svn: 300758
* [GISEL]: Move getConstantVReg to UtilsAditya Nandakumar2017-04-192-17/+17
| | | | | | NFCI llvm-svn: 300751
* [DAG] add splat vector support for 'and' in SimplifyDemandedBitsSanjay Patel2017-04-192-2/+2
| | | | | | | | | | | | | | | | | | | | | The patch itself is simple: stop discriminating against vectors in visitAnd() and again in SimplifyDemandedBits(). Some notes for reference: 1. We're not consistent about calls to SimplifyDemandedBits in the various visitXXX functions. Sometimes, we check if the RHS is a constant first. Other times (like here), we just dive in. 2. I'd like to break the vector shackles in steps for the sake of risk minimization, but we could make similar simultaneous changes in other places if we think that would be better. 3. I don't know what the intent of the changed tests in this patch was supposed to be, but since they wiggled in a positive way, I'm just going with that. :) 4. In the rotate tests, note that we can see through non-splat constants. This is a result of D24253. 5. My motivation for being here now is to make D31944 look better, so this is step 1 of N towards improving the vector codegen in that patch without writing any actual new code. Differential Revision: https://reviews.llvm.org/D32230 llvm-svn: 300725
* [DAG] Loop over remaining candidates on successful merge of stores ofNirav Dave2017-04-191-30/+43
| | | | | | extracted vectors types. NFCI. llvm-svn: 300688
* [GlobalISel] Support vector-of-pointers in LLTKristof Beyls2017-04-192-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes PR32471. As comment 10 on that bug report highlights (https://bugs.llvm.org//show_bug.cgi?id=32471#c10), there are quite a few different defendable design tradeoffs that could be made, including not representing pointers at all in LLT. I decided to go for representing vector-of-pointer as a concept in LLT, while keeping the size of the LLT type 64 bits (this is an increase from 48 bits before). My rationale for keeping pointers explicit is that on some targets probably it's very handy to have the distinction between pointer and non-pointer (e.g. 68K has a different register bank for pointers IIRC). If we keep a scalar pointer, it probably is easiest to also have a vector-of-pointers to keep LLT relatively conceptually clean and orthogonal, while we don't have a very strong reason to break that orthogonality. Once we gain more experience on the use of LLT, we can of course reconsider this direction. Rejecting vector-of-pointer types in the IRTranslator is also an option to avoid the crash reported in PR32471, but that is only a very short-term solution; also needs quite a bit of code tweaks in places, and is probably fragile. Therefore I didn't consider this the best option. llvm-svn: 300664
* [GlobalISel] Remove non-determinism from IRTranslator.Kristof Beyls2017-04-191-12/+16
| | | | | | | | | | | This showed up in r300535/r300537, which were reverted in r300538 due to some of the introduced tests in there failing on some bots, due to the non-determinism fixed in this commit. Re-committing r300535/r300537 will add 2 tests for the change in this commit. llvm-svn: 300663
* [X86] Keep EXTRACT_VECTOR_ELT result type as f128 for Android x86_64.Chih-Hung Hsieh2017-04-182-3/+6
| | | | | | | | | | Android x86_64 target uses f128 type and stores f128 values in %xmm* registers. SoftenFloatRes_EXTRACT_VECTOR_ELT should not convert result value from f128 to i128. Differential Revision: http://reviews.llvm.org/D32102 llvm-svn: 300583
* [APInt] Use lshrInPlace to replace lshr where possibleCraig Topper2017-04-185-21/+20
| | | | | | | | | | This patch uses lshrInPlace to replace code where the object that lshr is called on is being overwritten with the result. This adds an lshrInPlace(const APInt &) version as well. Differential Revision: https://reviews.llvm.org/D32155 llvm-svn: 300566
* [DAG] Improve store merge candidate pruning.Nirav Dave2017-04-181-0/+21
| | | | | | | | | | | | | | Remove non-consecutive stores from store merge candidate search as they cannot be merged and will prevent us from finding subsequent mergeable store cases. Reviewers: jyknight, bogner, javed.absar, spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32086 llvm-svn: 300561
* Revert "[GlobalISel] Support vector-of-pointers in LLT"Kristof Beyls2017-04-182-6/+5
| | | | | | | | | | | | | | | | This reverts r300535 and r300537. The newly added tests in test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll produces slightly different code between LLVM versions being built with different compilers. E.g., dependent on the compiler LLVM is built with, either one of the following can be produced: remark: <unknown>:0:0: unable to legalize instruction: %vreg0<def>(p0) = G_EXTRACT_VECTOR_ELT %vreg1, %vreg2; (in function: vector_of_pointers_extractelement) remark: <unknown>:0:0: unable to legalize instruction: %vreg2<def>(p0) = G_EXTRACT_VECTOR_ELT %vreg1, %vreg0; (in function: vector_of_pointers_extractelement) Non-determinism like this is clearly a bad thing, so reverting this until I can find and fix the root cause of the non-determinism. llvm-svn: 300538
* [GlobalISel] Support vector-of-pointers in LLTKristof Beyls2017-04-182-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes PR32471. As comment 10 on that bug report highlights (https://bugs.llvm.org//show_bug.cgi?id=32471#c10), there are quite a few different defendable design tradeoffs that could be made, including not representing pointers at all in LLT. I decided to go for representing vector-of-pointer as a concept in LLT, while keeping the size of the LLT type 64 bits (this is an increase from 48 bits before). My rationale for keeping pointers explicit is that on some targets probably it's very handy to have the distinction between pointer and non-pointer (e.g. 68K has a different register bank for pointers IIRC). If we keep a scalar pointer, it probably is easiest to also have a vector-of-pointers to keep LLT relatively conceptually clean and orthogonal, while we don't have a very strong reason to break that orthogonality. Once we gain more experience on the use of LLT, we can of course reconsider this direction. Rejecting vector-of-pointer types in the IRTranslator is also an option to avoid the crash reported in PR32471, but that is only a very short-term solution; also needs quite a bit of code tweaks in places, and is probably fragile. Therefore I didn't consider this the best option. llvm-svn: 300535
* PR32382: Fix emitting complex DWARF expressions.Adrian Prantl2017-04-1813-124/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DWARF specification knows 3 kinds of non-empty simple location descriptions: 1. Register location descriptions - describe a variable in a register - consist of only a DW_OP_reg 2. Memory location descriptions - describe the address of a variable 3. Implicit location descriptions - describe the value of a variable - end with DW_OP_stack_value & friends The existing DwarfExpression code is pretty much ignorant of these restrictions. This used to not matter because we only emitted very short expressions that we happened to get right by accident. This patch makes DwarfExpression aware of the rules defined by the DWARF standard and now chooses the right kind of location description for each expression being emitted. This would have been an NFC commit (for the existing testsuite) if not for the way that clang describes captured block variables. Based on how the previous code in LLVM emitted locations, DW_OP_deref operations that should have come at the end of the expression are put at its beginning. Fixing this means changing the semantics of DIExpression, so this patch bumps the version number of DIExpression and implements a bitcode upgrade. There are two major changes in this patch: I had to fix the semantics of dbg.declare for describing function arguments. After this patch a dbg.declare always takes the *address* of a variable as the first argument, even if the argument is not an alloca. When lowering a DBG_VALUE, the decision of whether to emit a register location description or a memory location description depends on the MachineLocation — register machine locations may get promoted to memory locations based on their DIExpression. (Future) optimization passes that want to salvage implicit debug location for variables may do so by appending a DW_OP_stack_value. For example: DBG_VALUE, [RBP-8] --> DW_OP_fbreg -8 DBG_VALUE, RAX --> DW_OP_reg0 +0 DBG_VALUE, RAX, DIExpression(DW_OP_deref) --> DW_OP_reg0 +0 All testcases that were modified were regenerated from clang. I also added source-based testcases for each of these to the debuginfo-tests repository over the last week to make sure that no synchronized bugs slip in. The debuginfo-tests compile from source and run the debugger. https://bugs.llvm.org/show_bug.cgi?id=32382 <rdar://problem/31205000> Differential Revision: https://reviews.llvm.org/D31439 llvm-svn: 300522
* [CodeGenPrepare] Fix crash due to an invalid CFGBrendon Cahoon2017-04-171-2/+8
| | | | | | | | | | | | | | | The splitIndirectCriticalEdges function generates and invalid CFG when the 'Target' basic block is a loop to itself. When this occurs, the code that updates the predecessor terminator needs to update the terminator in the split basic block. This occurs when there is an edge from block D back to D. Since D is split in to D0 and D1, the code needs to update the terminator in D1. But D1 is not in the OtherPreds vector, so it was not getting updated. Differential Revision: https://reviews.llvm.org/D32126 llvm-svn: 300480
* Distinguish between code pointer size and DataLayout::getPointerSize() in ↵Konstantin Zhuravlyov2017-04-175-17/+19
| | | | | | DWARF info generation llvm-svn: 300463
* [ProfileData] Unify getInstrProf*SectionName helpersVedant Kumar2017-04-151-1/+2
| | | | | | | | | | | | | | | | | | | | | | This is a version of D32090 that unifies all of the `getInstrProf*SectionName` helper functions. (Note: the build failures which D32090 would have addressed were fixed with r300352.) We should unify these helper functions because they are hard to use in their current form. E.g we recently introduced more helpers to fix section naming for COFF files. This scheme doesn't totally succeed at hiding low-level details about section naming, so we should switch to an API that is easier to maintain. This is not an NFC commit because it fixes llvm-cov's testing support for COFF files (this falls out of the API change naturally). This is an area where we lack tests -- I will see about adding one as a follow up. Testing: check-clang, check-profile, check-llvm. Differential Revision: https://reviews.llvm.org/D32097 llvm-svn: 300381
* [IR] Make paramHasAttr to use arg indices instead of attr indicesReid Kleckner2017-04-143-22/+20
| | | | | | | | | This avoids the confusing 'CS.paramHasAttr(ArgNo + 1, Foo)' pattern. Previously we were testing return value attributes with index 0, so I introduced hasReturnAttr() for that use case. llvm-svn: 300367
* [Profile] Make host tool aware of object format when quering prof section names Xinliang David Li2017-04-141-4/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D32073 llvm-svn: 300352
* Reorder StoreMergeCandidates to run faster. NFCI.Nirav Dave2017-04-141-20/+23
| | | | llvm-svn: 300321
* Fix for PR#30562: Selection DAG error: Detected cycle in SelectionDAG.Andrew V. Tischenko2017-04-141-2/+5
| | | | | | Patch by Dinar Temirbulatov llvm-svn: 300314
* This patch closes PR#32216: Better testing of schedule model instruction ↵Andrew V. Tischenko2017-04-143-11/+152
| | | | | | | | latencies/throughputs. The details are here: https://reviews.llvm.org/D30941 llvm-svn: 300311
* LLVMCodeGen: Add ProfileData into deps corresponding to r300277.NAKAMURA Takumi2017-04-141-1/+1
| | | | llvm-svn: 300289
* [Profile] PE binary coverage bug fixXinliang David Li2017-04-131-1/+3
| | | | | | | | PR/32584 Differential Revision: https://reviews.llvm.org/D32023 llvm-svn: 300277
* [DAG] Fold away temporary vector in store candidate merge NFC.Nirav Dave2017-04-131-14/+11
| | | | llvm-svn: 300241
* Use methods to access data stored with frame instructionsSerge Pavlov2017-04-133-26/+8
| | | | | | | | | | | | | Instructions CALLSEQ_START..CALLSEQ_END and their target dependent counterparts keep data like frame size, stack adjustment etc. These data are accessed by getOperand using hard coded indices. It is error prone way. This change implements the access by special methods, which improve readability and allow changing data representation without massive changes of index values. Differential Revision: https://reviews.llvm.org/D31953 llvm-svn: 300196
* [SelectionDAG] Use APInt move assignment to avoid 2 memory allocations and ↵Craig Topper2017-04-121-2/+2
| | | | | | copies when bit width is larger than 64-bits. llvm-svn: 300091
* CodeGen: BlockPlacement: Add comment about DenseMap Safety.Kyle Butt2017-04-121-0/+3
| | | | | | | | | The use of a DenseMap in precomputeTriangleChains does not cause non-determinism, even though it is iterated over, as the only thing the iteration does is to insert entries into a new DenseMap, which is not iterated. Comment only change. llvm-svn: 300088
* MachineScheduler: Skip acyclic latency heuristic for in-order coresMatthias Braun2017-04-121-1/+1
| | | | | | | | | | | | | | | | | The current heuristic is triggered on `InFlightCount > BufferLimit` which isn't really helpful on in-order cores where BufferLimit is zero. Note that we already get latency hiding effects for in order cores by instructions staying in the pending queue on stalls; The additional latency scheduling heuristics only have minimal effects after that while occasionally increasing register pressure too much resulting in extra spills. My motivation here is additional spills/reloads ending up in a loop in 464.h264ref / BlockMotionSearch function resulting in a 4% overal regression on an in order core. rdar://30264380 llvm-svn: 300083
* Remove redundant type castsSerge Pavlov2017-04-121-12/+8
| | | | llvm-svn: 300063
* [MachineBlockPlacment] Add an assert to ensure there is no order dependency ↵Benjamin Kramer2017-04-121-3/+7
| | | | | | on DenseMap iteration order. llvm-svn: 300060
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