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* AnalyzeBranch doesn't change which successors a bb has, just the orderRafael Espindola2011-06-121-4/+11
| | | | | | | | | | | | | | | | | | we try to branch to them. Before we were creating successor lists with duplicated entries. Fixing that found a bug in isBlockOnlyReachableByFallthrough that would causes it to return the wrong answer for ----------- ... jne foo jmp bar foo: ---------- llvm-svn: 132882
* Revert r132871.Chad Rosier2011-06-111-1/+1
| | | | llvm-svn: 132872
* Typo.Chad Rosier2011-06-111-1/+1
| | | | llvm-svn: 132871
* 80-col cleanups.Eric Christopher2011-06-101-6/+5
| | | | llvm-svn: 132863
* Removed tabs. Also fixed my editor...Rafael Espindola2011-06-101-3/+2
| | | | llvm-svn: 132857
* Rename the ParmContext enum values to make a bit more sense and add a smallCameron Zwarich2011-06-101-1/+1
| | | | | | comment on their meaning. llvm-svn: 132854
* Remove tabs.Cameron Zwarich2011-06-101-2/+2
| | | | llvm-svn: 132853
* Remove a pointless const_cast.Cameron Zwarich2011-06-101-1/+1
| | | | llvm-svn: 132852
* Remove duplicated test.Rafael Espindola2011-06-101-4/+3
| | | | | | Thanks Bob Wilson for noticing it! llvm-svn: 132851
* Ensure that EmitGlobalVariable is correctly differentiating between declarationsChad Rosier2011-06-101-1/+1
| | | | | | | | and definitions when emitting global variables. This was causing global declarations to be emitted as if they were definitions. Fixes <rdar://problem/9429892>. llvm-svn: 132825
* Make the optional verification step more strict.Rafael Espindola2011-06-091-1/+8
| | | | llvm-svn: 132822
* Avoid a gcc warning about multiline comments.Rafael Espindola2011-06-091-6/+6
| | | | llvm-svn: 132821
* On last fix to the early tail duplication.Rafael Espindola2011-06-091-4/+60
| | | | | | | | With this I am able to bootstrap clang with early tail duplication enabled for any small bb and setting tail-dup-size to a relatively large value(8) to stress this code. llvm-svn: 132816
* Also consider phi nodes when deciding if a register is live out.Rafael Espindola2011-06-091-10/+34
| | | | llvm-svn: 132814
* Change this DAGCombine to build AND of SHR instead of SHR of AND; this ↵Eli Friedman2011-06-091-15/+16
| | | | | | | | matches the ordering we prefer in instcombine. Part of rdar://9562809. The potential DAGCombine which enforces this more generally messes up some other very fragile patterns, so I'm leaving that alone, at least for now. llvm-svn: 132809
* AnalyzeBranch modifies the bb, but we don't want to modify a bb withRafael Espindola2011-06-091-7/+6
| | | | | | eh edges. Swap the order of the checks to avoid it. llvm-svn: 132806
* A PHI in this basic block is a use in another basic block.Rafael Espindola2011-06-091-1/+1
| | | | llvm-svn: 132805
* Refactor some checks into shouldTailDuplicate. Update comments.Rafael Espindola2011-06-091-18/+29
| | | | | | No functionality change. llvm-svn: 132798
* Recommit r132764 since it didn't cause the windows buildbot failures.Eric Christopher2011-06-091-0/+2
| | | | llvm-svn: 132776
* Temporarily revert 132764 to see if it fixes the Windows buildbot.Eric Christopher2011-06-091-2/+0
| | | | llvm-svn: 132771
* If the alignment of the byval argument is greater than the alignmentEric Christopher2011-06-091-0/+2
| | | | | | | | | of the frame then increase the maximum alignment of the frame to match. Fixes PR6965 llvm-svn: 132764
* Add a parameter to CCState so that it can access the MachineFunction.Eric Christopher2011-06-083-14/+19
| | | | | | | | No functional change. Part of PR6965 llvm-svn: 132763
* Remove a temporary test case probe in CheckForLiveRegDef.Andrew Trick2011-06-081-1/+0
| | | | llvm-svn: 132751
* Fix count.Rafael Espindola2011-06-081-1/+1
| | | | llvm-svn: 132749
* Count how many phis we are creating.Rafael Espindola2011-06-081-0/+2
| | | | llvm-svn: 132748
* Fix an issue where the two-address conversion pass incorrectly rewrites untiedCameron Zwarich2011-06-071-9/+16
| | | | | | operands to an early clobber register. This fixes <rdar://problem/9566076>. llvm-svn: 132738
* Fix a silly error I introduce in r131951.Rafael Espindola2011-06-071-4/+1
| | | | | | Fixes PR10095. llvm-svn: 132735
* Fix a merge bug in preRAsched for handling physreg aliases.Andrew Trick2011-06-071-4/+6
| | | | | | | I've been sitting on this long enough trying to find a test case. I think the fix should go in now, but I'll keep working on the test case. llvm-svn: 132701
* Simplify local live range splitting's safeguard to fix PR10070.Jakob Stoklund Olesen2011-06-061-87/+57
| | | | | | | | | | | | | | | When local live range splitting creates a live range with the same number of instructions as the old range, mark it as RS_Local. When such a range is seen again, require that it be split in a way that reduces the number of instructions. That guarantees we are making progress while still being able to perform 3 -> 2+3 splits as required by PR10070. This also means that the PrevSlot map is no longer needed. This was also used to estimate new spill weights, but that is no longer necessary after slotIndexes::insertMachineInstrInMaps() got the extra Late insertion argument. llvm-svn: 132697
* Get allocation orders from RegisterClassInfo when possible.Jakob Stoklund Olesen2011-06-062-23/+52
| | | | | | | | | | | | Only target-dependent hints require callbacks. The RCI allocation order has CSR aliases last according to their order of appearance in the getCalleeSavedRegs list. This can depend on the calling convention. This way, AllocationOrder::next doesn't have to check for reserved registers, and CSRs are always allocated last, even with weird calling conventions. llvm-svn: 132690
* Add methods to support the integer-promotion of vector types. Methods toNadav Rotem2011-06-063-0/+192
| | | | | | legalize SDNodes such as BUILD_VECTOR, EXTRACT_VECTOR_ELT, etc. llvm-svn: 132689
* Avoid FGETSIGN of 80-bit types. Fixes PR10085.Stuart Hastings2011-06-061-6/+8
| | | | llvm-svn: 132681
* Don't try to be clever, just preserve the target's allocation order.Jakob Stoklund Olesen2011-06-061-11/+6
| | | | | | | | | | | | | | | The order of registers returned by getCalleeSavedRegs is used to lay out the fixed stack slots for CSRs. Some targets like their CSRs used from one end, and some targets want them used from the other end. When computing an allocation order, simply preserve the relative ordering of CSRs that the target specifies in its allocation order. Reordering CSRs would break some targets, ARM in particular. We still place volatiles before the CSRs, providing slightly better results with different calling conventions. llvm-svn: 132680
* PR10077: fix fast-isel of extractvalue of aggregate constants.Eli Friedman2011-06-061-1/+3
| | | | llvm-svn: 132676
* Use path API for path concatenation.Benjamin Kramer2011-06-051-5/+3
| | | | llvm-svn: 132668
* TypeLegalizer: Add support for passing of vector-promoted types in registers ↵Nadav Rotem2011-06-041-2/+40
| | | | | | (copyFromParts/copyToParts). llvm-svn: 132649
* TypeLegalizer: Fix a bug in the promotion of elements of integer vectors.Nadav Rotem2011-06-041-16/+22
| | | | | | | | | (only happens when using the -promote-elements option). The correct legalization order is to first try to promote element. Next, we try to widen vectors. llvm-svn: 132648
* Switch AllocationOrder to using RegisterClassInfo instead of a BitVectorJakob Stoklund Olesen2011-06-035-22/+18
| | | | | | | | | of reserved registers. Use RegisterClassInfo in RABasic as well. This slightly changes som allocation orders because RegisterClassInfo puts CSR aliases last. llvm-svn: 132581
* Preserve the original ordering when a CSR has multiple aliases.Jakob Stoklund Olesen2011-06-031-2/+14
| | | | | | | | Previously, these aliases would be ordered alphabetically. (BH, BL) Print out the computed allocation orders. llvm-svn: 132580
* Add a TODO about memory operands.Eric Christopher2011-06-031-1/+5
| | | | llvm-svn: 132559
* Avoid calling TRI->getAllocatableSet in RAFast.Jakob Stoklund Olesen2011-06-022-9/+23
| | | | | | | | | | | | | | When compiling a program with lots of small functions like 483.xalancbmk, this makes RAFast 11% faster. Add some comments to clarify the difference between unallocatable and reserved registers. It's quite subtle. The fast register allocator depends on EFLAGS' not being allocatable on x86. That way it can completely avoid tracking liveness, and it won't mind when there are multiple uses of a single def. llvm-svn: 132514
* Have LowerOperandForConstraint handle multiple character constraints.Eric Christopher2011-06-022-3/+7
| | | | | | Part of rdar://9119939 llvm-svn: 132510
* Make it possible to have unallocatable register classes.Jakob Stoklund Olesen2011-06-021-0/+2
| | | | | | | | | | | | | | | Some register classes are only used for instruction operand constraints. They should never be used for virtual registers. Previously, those register classes were given an empty allocation order, but now you can say 'let isAllocatable=0' in the register class definition. TableGen calculates if a register is part of any allocatable register class, and makes that information available in TargetRegisterDesc::inAllocatableClass. The goal here is to eliminate use cases for overriding allocation_order_* methods. llvm-svn: 132508
* Just use a SmallVector.Jakob Stoklund Olesen2011-06-022-2/+3
| | | | | | | | | I was confused whether new uint8_t[] would zero-initialize the returned array, and it seems that so is gcc-4.0. This should fix the test failures on darwin 9. llvm-svn: 132500
* Remove dead code.Devang Patel2011-06-021-8/+3
| | | | llvm-svn: 132488
* Update DBG_VALUEs while breaking anti dependencies.Devang Patel2011-06-028-29/+42
| | | | llvm-svn: 132487
* During post RA scheduling, do not try to chase reg defs. to preserve ↵Devang Patel2011-06-022-39/+32
| | | | | | | | DBG_VALUEs. This approach has several downsides, for example, it does not work when dbg value is a constant integer, it does not work if reg is defined more than once, it places end of debug value range markers in the wrong place. It even causes misleading incorrect debug info when duplicate DBG_VALUE instructions point to same reg def. Instead, use simpler approach and let DBG_VALUE follow its predecessor instruction. After live debug value analysis pass, all DBG_VALUE instruction are placed at the right place. Thanks Jakob for the hint! llvm-svn: 132483
* Revert 132424 to fix PR10068.Rafael Espindola2011-06-021-5/+4
| | | | llvm-svn: 132479
* Use RegisterClassInfo::getOrder in RAFast.Jakob Stoklund Olesen2011-06-021-10/+7
| | | | | | | This saves two virtual function calls and an Allocatable BitVector test, making RAFast run 2% faster. llvm-svn: 132471
* Start with a zeroed CSRNum map.Benjamin Kramer2011-06-021-1/+1
| | | | | | Found by valgrind. llvm-svn: 132457
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