| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
| |
llvm-svn: 135448
|
|
|
|
|
|
| |
library.
llvm-svn: 135443
|
|
|
|
|
|
| |
better location welcome).
llvm-svn: 135438
|
|
|
|
|
|
|
|
|
| |
ambiguity
errors like the one corrected by r135261. Migrate all LLVM callers of the old
constructor to the new one.
llvm-svn: 135431
|
|
|
|
|
|
|
|
|
| |
to MCRegisterInfo. Also initialize the mapping at construction time.
This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.
llvm-svn: 135424
|
|
|
|
|
|
|
|
| |
at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases.
[take 2]
llvm-svn: 135423
|
|
|
|
|
|
|
|
|
|
|
|
| |
When splitting a live range immediately before an LDR_POST instruction
that redefines the address register, make sure to use the correct value
number in leaveIntvBefore.
We need the value number entering the instruction.
<rdar://problem/9793765>
llvm-svn: 135413
|
|
|
|
|
|
|
|
| |
previously explicit non-default constructors were used.
Mostly mechanical with some manual reformatting.
llvm-svn: 135390
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
When trying to rematerialize a value before an instruction that has an
early-clobber redefine of the virtual register, make sure to look up the
correct value number.
Early-clobber defs are moved one slot back, so getBaseIndex is needed to
find the used value number.
Bugpoint was unable to reduce the test case for this, see PR10388.
llvm-svn: 135378
|
|
|
|
| |
llvm-svn: 135375
|
|
|
|
| |
llvm-svn: 135362
|
|
|
|
| |
llvm-svn: 135354
|
|
|
|
| |
llvm-svn: 135352
|
|
|
|
| |
llvm-svn: 135339
|
|
|
|
|
|
|
| |
This should unbreak the build-self-4-mingw32 tester. I have a very
complicated test case that I will try to clean up.
llvm-svn: 135329
|
|
|
|
| |
llvm-svn: 135320
|
|
|
|
|
|
| |
and just use the ones from TargetLowering directly.
llvm-svn: 135318
|
|
|
|
| |
llvm-svn: 135311
|
|
|
|
|
|
|
|
|
|
|
| |
This gets rid of some of the gory splitting details in RAGreedy and
makes them available to future SplitKit clients.
Slightly generalize the functionality to support multi-way splitting.
Specifically, SplitEditor::splitLiveThroughBlock() supports switching
between different register intervals in a block.
llvm-svn: 135307
|
|
|
|
| |
llvm-svn: 135305
|
|
|
|
|
|
| |
lexical scope.
llvm-svn: 135302
|
|
|
|
| |
llvm-svn: 135278
|
|
|
|
| |
llvm-svn: 135265
|
|
|
|
| |
llvm-svn: 135254
|
|
|
|
| |
llvm-svn: 135232
|
|
|
|
|
|
| |
MCTargetDesc to prepare for next round of changes.
llvm-svn: 135219
|
|
|
|
| |
llvm-svn: 135212
|
|
|
|
|
|
| |
Improve DbgScope->dump() output.
llvm-svn: 135207
|
|
|
|
|
|
|
|
|
| |
when determining validity of matching constraint. Allow i1
types access to the GR8 reg class for x86.
Fixes PR10352 and rdar://9777108
llvm-svn: 135180
|
|
|
|
| |
llvm-svn: 135154
|
|
|
|
|
|
|
|
|
|
|
| |
During type legalization we often use the SIGN_EXTEND_INREG SDNode.
When this SDNode is legalized during the LegalizeVector phase, it is
scalarized because non-simple types are automatically marked to be expanded.
In this patch we add support for lowering SIGN_EXTEND_INREG manually.
This fixes CodeGen/X86/vec_sext.ll when running with the '-promote-elements'
flag.
llvm-svn: 135144
|
|
|
|
| |
llvm-svn: 135143
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Original commit message:
Count references to interference cache entries.
Each InterferenceCache::Cursor instance references a cache entry. A
non-zero reference count guarantees that the entry won't be reused for a
new register.
This makes it possible to have multiple live cursors examining
interference for different physregs.
The total number of live cursors into a cache must be kept below
InterferenceCache::getMaxCursors().
Code generation should be unaffected by this change, and it doesn't seem
to affect the cache replacement strategy either.
llvm-svn: 135130
|
|
|
|
| |
llvm-svn: 135127
|
|
|
|
|
|
| |
simple SETNE is sufficient.
llvm-svn: 135126
|
|
|
|
|
|
| |
much as possible.
llvm-svn: 135124
|
|
|
|
|
|
| |
Fixes rdar://9761830
llvm-svn: 135123
|
|
|
|
| |
llvm-svn: 135122
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Each InterferenceCache::Cursor instance references a cache entry. A
non-zero reference count guarantees that the entry won't be reused for a
new register.
This makes it possible to have multiple live cursors examining
interference for different physregs.
The total number of live cursors into a cache must be kept below
InterferenceCache::getMaxCursors().
Code generation should be unaffected by this change, and it doesn't seem
to affect the cache replacement strategy either.
llvm-svn: 135121
|
|
|
|
| |
llvm-svn: 135118
|
|
|
|
|
|
|
|
|
|
| |
The cache entry referenced by the best split candidate could become
clobbered by an unsuccessful candidate.
The correct fix here is to use reference counts on the cache entries.
Coming up.
llvm-svn: 135113
|
|
|
|
| |
llvm-svn: 135111
|
|
|
|
| |
llvm-svn: 135110
|
|
|
|
| |
llvm-svn: 135096
|
|
|
|
|
|
|
|
|
| |
Some pysical registers create split solutions that would spill anywhere.
They should not even be considered in future multi-way global splits.
This does not affect code generation (yet).
llvm-svn: 135080
|
|
|
|
|
|
|
| |
This is in preparation of supporting multiple global split candidates in
a single live range split operation.
llvm-svn: 135074
|
|
|
|
| |
llvm-svn: 135068
|
|
|
|
| |
llvm-svn: 135040
|
|
|
|
|
|
| |
StructType::get() and TargetData::getIntPtrType().
llvm-svn: 134982
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
an assert on Darwin llvm-gcc builds.
Assertion failed: (castIsValid(op, S, Ty) && "Invalid cast!"), function Create, file /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.llvm-gcc-i386-darwin9-RA/llvm.src/lib/VMCore/Instructions.cpp, li\
ne 2067.
etc.
http://smooshlab.apple.com:8013/builders/llvm-gcc-i386-darwin9-RA/builds/2354
--- Reverse-merging r134893 into '.':
U include/llvm/Target/TargetData.h
U include/llvm/DerivedTypes.h
U tools/bugpoint/ExtractFunction.cpp
U unittests/Support/TypeBuilderTest.cpp
U lib/Target/ARM/ARMGlobalMerge.cpp
U lib/Target/TargetData.cpp
U lib/VMCore/Constants.cpp
U lib/VMCore/Type.cpp
U lib/VMCore/Core.cpp
U lib/Transforms/Utils/CodeExtractor.cpp
U lib/Transforms/Instrumentation/ProfilingUtils.cpp
U lib/Transforms/IPO/DeadArgumentElimination.cpp
U lib/CodeGen/SjLjEHPrepare.cpp
--- Reverse-merging r134888 into '.':
G include/llvm/DerivedTypes.h
U include/llvm/Support/TypeBuilder.h
U include/llvm/Intrinsics.h
U unittests/Analysis/ScalarEvolutionTest.cpp
U unittests/ExecutionEngine/JIT/JITTest.cpp
U unittests/ExecutionEngine/JIT/JITMemoryManagerTest.cpp
U unittests/VMCore/PassManagerTest.cpp
G unittests/Support/TypeBuilderTest.cpp
U lib/Target/MBlaze/MBlazeIntrinsicInfo.cpp
U lib/Target/Blackfin/BlackfinIntrinsicInfo.cpp
U lib/VMCore/IRBuilder.cpp
G lib/VMCore/Type.cpp
U lib/VMCore/Function.cpp
G lib/VMCore/Core.cpp
U lib/VMCore/Module.cpp
U lib/AsmParser/LLParser.cpp
U lib/Transforms/Utils/CloneFunction.cpp
G lib/Transforms/Utils/CodeExtractor.cpp
U lib/Transforms/Utils/InlineFunction.cpp
U lib/Transforms/Instrumentation/GCOVProfiling.cpp
U lib/Transforms/Scalar/ObjCARC.cpp
U lib/Transforms/Scalar/SimplifyLibCalls.cpp
U lib/Transforms/Scalar/MemCpyOptimizer.cpp
G lib/Transforms/IPO/DeadArgumentElimination.cpp
U lib/Transforms/IPO/ArgumentPromotion.cpp
U lib/Transforms/InstCombine/InstCombineCompares.cpp
U lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
U lib/Transforms/InstCombine/InstCombineCalls.cpp
U lib/CodeGen/DwarfEHPrepare.cpp
U lib/CodeGen/IntrinsicLowering.cpp
U lib/Bitcode/Reader/BitcodeReader.cpp
llvm-svn: 134949
|