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* Enhance the truncstore optimization code to handle shiftedChris Lattner2007-10-131-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | values and propagate demanded bits through them in simple cases. This allows this code: void foo(char *P) { strcpy(P, "abc"); } to compile to: _foo: ldrb r3, [r1] ldrb r2, [r1, #+1] ldrb r12, [r1, #+2]! ldrb r1, [r1, #+1] strb r1, [r0, #+3] strb r2, [r0, #+1] strb r12, [r0, #+2] strb r3, [r0] bx lr instead of: _foo: ldrb r3, [r1, #+3] ldrb r2, [r1, #+2] orr r3, r2, r3, lsl #8 ldrb r2, [r1, #+1] ldrb r1, [r1] orr r2, r1, r2, lsl #8 orr r3, r2, r3, lsl #16 strb r3, [r0] mov r2, r3, lsr #24 strb r2, [r0, #+3] mov r2, r3, lsr #16 strb r2, [r0, #+2] mov r3, r3, lsr #8 strb r3, [r0, #+1] bx lr testcase here: test/CodeGen/ARM/truncstore-dag-combine.ll This also helps occasionally for X86 and other cases not involving unaligned load/stores. llvm-svn: 42954
* Add a simple optimization to simplify the input toChris Lattner2007-10-132-1/+43
| | | | | | | truncate and truncstore instructions, based on the knowledge that they don't demand the top bits. llvm-svn: 42952
* Local spiller optimization: Evan Cheng2007-10-132-4/+54
| | | | | | | | | | | | | | | | | | | Turn this: movswl %ax, %eax movl %eax, -36(%ebp) xorl %edi, -36(%ebp) into movswl %ax, %eax xorl %edi, %eax movl %eax, -36(%ebp) by unfolding the load / store xorl into an xorl and a store when we know the value in the spill slot is available in a register. This doesn't change the number of instructions but reduce the number of times memory is accessed. Also unfold some load folding instructions and reuse the value when similar situation presents itself. llvm-svn: 42947
* Optionally create a MachineInstr without default implicit operands.Evan Cheng2007-10-131-4/+5
| | | | llvm-svn: 42945
* Corrected many typing errors. And removed 'nest' parameter handlingArnold Schwaighofer2007-10-121-2/+2
| | | | | | | for fastcc from X86CallingConv.td. This means that nested functions are not supported for calling convention 'fastcc'. llvm-svn: 42934
* ppc long double. Implement fabs and fneg.Dale Johannesen2007-10-121-0/+16
| | | | llvm-svn: 42924
* Implement i64->ppcf128 conversions.Dale Johannesen2007-10-121-1/+20
| | | | llvm-svn: 42919
* Did mean to leave this in. INSERT_SUBREG isn't being coalesced yet.Evan Cheng2007-10-121-2/+1
| | | | llvm-svn: 42916
* Change the names used for internal labels to use the currentDan Gohman2007-10-121-19/+19
| | | | | | | | | function symbol name instead of a codegen-assigned function number. Thanks Evan! :-) llvm-svn: 42908
* Fix some corner cases with vectors in copyToRegs and copyFromRegs.Dan Gohman2007-10-121-1/+16
| | | | llvm-svn: 42907
* Add support to SplitVectorOp for powi, where the second operandDan Gohman2007-10-121-0/+6
| | | | | | is a scalar integer. llvm-svn: 42906
* Restrict EXTRACT_SUBREG coalescing to avoid negative performance impact.Evan Cheng2007-10-121-1/+6
| | | | llvm-svn: 42903
* EXTRACT_SUBREG coalescing support. The coalescer now treats EXTRACT_SUBREG likeEvan Cheng2007-10-127-231/+371
| | | | | | | | | (almost) a register copy. However, it always coalesced to the register of the RHS (the super-register). All uses of the result of a EXTRACT_SUBREG are sub- register uses which adds subtle complications to load folding, spiller rewrite, etc. llvm-svn: 42899
* Some clean up.Evan Cheng2007-10-121-3/+0
| | | | llvm-svn: 42898
* PPC long double. Implement a couple more conversions.Dale Johannesen2007-10-121-0/+35
| | | | llvm-svn: 42888
* Add intrinsics for sin, cos, and pow. These use llvm_anyfloat_ty, and soDan Gohman2007-10-121-0/+16
| | | | | | | may be overloaded with vector types. And add a testcase for codegen for these. llvm-svn: 42885
* Codegen support for vector intrinsics.Dan Gohman2007-10-111-27/+114
| | | | | | | | | | | | Factor out the code that expands the "nasty scalar code" for unrolling vectors into a separate routine, teach it how to handle mixed vector/scalar operands, as seen in powi, and use it for several operators, including sin, cos, powi, and pow. Add support in SplitVectorOp for fpow, fpowi and for several unary operators. llvm-svn: 42884
* Implement ppc long double->uint conversion.Dale Johannesen2007-10-112-3/+58
| | | | | | Make ppc long double constants print. llvm-svn: 42882
* Add runtime library names for pow.Dan Gohman2007-10-111-0/+4
| | | | llvm-svn: 42880
* Add an ISD::FPOW node type.Dan Gohman2007-10-111-0/+1
| | | | llvm-svn: 42879
* Added tail call optimization to the x86 back end. It can beArnold Schwaighofer2007-10-111-0/+48
| | | | | | | | | | | enabled by passing -tailcallopt to llc. The optimization is performed if the following conditions are satisfied: * caller/callee are fastcc * elf/pic is disabled OR elf/pic enabled + callee is in module + callee has visibility protected or hidden llvm-svn: 42870
* Next PPC long double bits. First cut at constants.Dale Johannesen2007-10-111-0/+8
| | | | | | | | | No compile-time support for constant operations yet, just format transformations. Make readers and writers work. Split constants into 2 doubles in Legalize. llvm-svn: 42865
* Correct swapped arguments to getConstant.Duncan Sands2007-10-101-1/+1
| | | | llvm-svn: 42824
* Next PPC long double bits: ppcf128->i32 conversion.Dale Johannesen2007-10-102-2/+26
| | | | | | | Surprisingly complicated. Adds getTargetNode for 2 outputs, no inputs (missing). llvm-svn: 42822
* Bad choice of variable name.Evan Cheng2007-10-101-2/+2
| | | | llvm-svn: 42821
* Fix an extremely stupid bug that prevented first round of coalescing ↵Evan Cheng2007-10-091-1/+2
| | | | | | (physical registers only) from happening. llvm-svn: 42820
* Call getFunctionNumber() instead of referencing FunctionNumber directly,Dan Gohman2007-10-081-1/+1
| | | | | | for consistency. llvm-svn: 42769
* Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} toDan Gohman2007-10-082-40/+140
| | | | | | | | use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code associated with these operators into target-independent in LegalizeDAG.cpp and TargetLowering.cpp. llvm-svn: 42762
* DAGCombiner support for UDIVREM/SDIVREM and UMUL_LOHI/SMUL_LOHI. Dan Gohman2007-10-081-17/+137
| | | | | | | | | Check if one of the two results unneeded so see if a simpler operator could bs used. Also check to see if each of the two computations could be simplified if they were split into separate operators. Factor out the code that calls visit() so that it can be used for this purpose. llvm-svn: 42759
* Add convenience overloads of SelectionDAG::getNode that take a SDVTListDan Gohman2007-10-081-0/+36
| | | | | | and individual SDOperand operands. llvm-svn: 42753
* In -debug mode, dump SelectionDAGs both before and after theDan Gohman2007-10-081-1/+7
| | | | | | optimization passes. llvm-svn: 42749
* Kill cycle of an live range is always the last use index + 1.Evan Cheng2007-10-081-1/+1
| | | | llvm-svn: 42742
* convertFromInteger, as originally written, expected sign-extendedNeil Booth2007-10-072-3/+3
| | | | | | | | input. APInt unfortunately zero-extends signed integers, so Dale modified the function to expect zero-extended input. Make this assumption explicit in the function name. llvm-svn: 42732
* Reapply 42677.Evan Cheng2007-10-061-3/+52
| | | | llvm-svn: 42692
* revert evan's patch until the header is committedChris Lattner2007-10-061-52/+3
| | | | llvm-svn: 42686
* Added DAG xforms. e.g.Evan Cheng2007-10-061-3/+52
| | | | | | | | (vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr) (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr) Remove x86 specific patterns. llvm-svn: 42677
* Next powerpc long double bits. Comparisons work,Dale Johannesen2007-10-061-28/+56
| | | | | | although not well, and shortening FP converts. llvm-svn: 42672
* First round of ppc long double. call/return andDale Johannesen2007-10-052-31/+86
| | | | | | | | | basic arithmetic works. Rename RTLIB long double functions to distinguish different flavors of long double; the lib functions have different names, alas. llvm-svn: 42644
* Legalize support for MUL_LOHI and DIVREM.Dan Gohman2007-10-051-0/+10
| | | | llvm-svn: 42636
* Fix a typo in a comment.Dan Gohman2007-10-051-1/+1
| | | | llvm-svn: 42635
* Provide names for MUL_LOHI and DIVREM operators.Dan Gohman2007-10-051-0/+4
| | | | llvm-svn: 42634
* Chain producing nodes cannot be moved, not chain reading nodes.Evan Cheng2007-10-051-5/+7
| | | | llvm-svn: 42627
* Oops. Didn't mean to leave this in.Evan Cheng2007-10-051-1/+0
| | | | llvm-svn: 42626
* If a node that defines a physical register that is expensive to copy. TheEvan Cheng2007-10-052-47/+165
| | | | | | | | | scheduler will try a number of tricks in order to avoid generating the copies. This may not be possible in case the node produces a chain value that prevent movement. Try unfolding the load from the node before to allow it to be moved / cloned. llvm-svn: 42625
* Add a variant of getTargetNode() that takes a vector of MVT::ValueType.Evan Cheng2007-10-051-0/+7
| | | | llvm-svn: 42620
* Silence a warning.Evan Cheng2007-10-051-1/+1
| | | | llvm-svn: 42619
* Use empty() member functions when that's what's being tested for insteadDan Gohman2007-10-034-15/+13
| | | | | | of comparing begin() and end(). llvm-svn: 42585
* Rewrite sqrt and powi to use anyfloat. By popular demand.Dale Johannesen2007-10-022-39/+30
| | | | llvm-svn: 42537
* Fix stride computations for long double arrays.Dale Johannesen2007-10-012-3/+7
| | | | llvm-svn: 42508
* Move the code that emits the .file directives so that it runs after theDan Gohman2007-10-011-16/+17
| | | | | | SourceFiles list is fully filled in so that it sees all of the files. llvm-svn: 42506
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