summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
Commit message (Collapse)AuthorAgeFilesLines
* Implement target independent TLS compatible with glibc's emutls.c.Chih-Hung Hsieh2015-07-283-29/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'common' section TLS is not implemented. Current C/C++ TLS variables are not placed in common section. DWARF debug info to get the address of TLS variables is not generated yet. clang and driver changes in http://reviews.llvm.org/D10524 Added -femulated-tls flag to select the emulated TLS model, which will be used for old targets like Android that do not support ELF TLS models. Added TargetLowering::LowerToTLSEmulatedModel as a target-independent function to convert a SDNode of TLS variable address to a function call to __emutls_get_address. Added into lib/Target/*/*ISelLowering.cpp to call LowerToTLSEmulatedModel for TLSModel::Emulated. Although all targets supporting ELF TLS models are enhanced, emulated TLS model has been tested only for Android ELF targets. Modified AsmPrinter.cpp to print the emutls_v.* and emutls_t.* variables for emulated TLS variables. Modified DwarfCompileUnit.cpp to skip some DIE for emulated TLS variabls. TODO: Add proper DIE for emulated TLS variables. Added new unit tests with emulated TLS. Differential Revision: http://reviews.llvm.org/D10522 llvm-svn: 243438
* Changes for MachineBasicBlock to use SortedVector for LiveIns.Puyan Lotfi2015-07-281-5/+0
| | | | llvm-svn: 243389
* Move the Target way of overriding DAG Scheduler to a target hookMehdi Amini2015-07-281-8/+6
| | | | | | | | | | | | | | | Summary: The previous way of overriding it was relying on calling "setDefault" on the global registry, which implies global mutable state. Reviewers: echristo, atrick Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11538 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 243388
* MIR Serialization: Serialize the unnamed basic block references.Alex Lorenz2015-07-276-7/+93
| | | | | | | | | | | | This commit serializes the references from the machine basic blocks to the unnamed basic blocks. This commit adds a new attribute to the machine basic block's YAML mapping called 'ir-block'. This attribute contains the actual reference to the basic block. Reviewers: Duncan P. N. Exon Smith llvm-svn: 243340
* MIR Serialization: Serialize the '.cfi_def_cfa_register' CFI instruction.Alex Lorenz2015-07-274-0/+15
| | | | llvm-svn: 243322
* MIR Parser: Rename the standalone parsing methods. NFC.Alex Lorenz2015-07-271-6/+7
| | | | | | | | This commit renames the methods 'parseMBB' and 'parseNamedRegister' to 'parseStandaloneMBB' and 'parseStandaloneNamedRegister' in order for their names to be consistent with the method 'parseStandaloneVirtualRegister'. llvm-svn: 243319
* Revert "[PeepholeOptimizer] Look through PHIs to find additional register ↵Bruno Cardoso Lopes2015-07-271-275/+82
| | | | | | | | sources" Still breaks some ARM buildbots. This reverts r243271. llvm-svn: 243318
* move combineRepeatedFPDivisors logic into a helper function; NFCISanjay Patel2015-07-271-42/+57
| | | | llvm-svn: 243293
* Reset the virtual registers in liveins when clearing the virtual registers.Alex Lorenz2015-07-271-0/+2
| | | | | | | | | This commit zeroes out the virtual register references in the machine function's liveins in the class 'MachineRegisterInfo' when the virtual register definitions are cleared. Reviewers: Matthias Braun llvm-svn: 243290
* MIR Serialization: Serialize the machine function's liveins.Alex Lorenz2015-07-274-0/+52
| | | | | Reviewers: Duncan P. N. Exon Smith llvm-svn: 243288
* [PeepholeOptimizer] Look through PHIs to find additional register sourcesBruno Cardoso Lopes2015-07-271-82/+275
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reapply r242295 with fixes in the implementation. - Teaches the ValueTracker in the PeepholeOptimizer to look through PHI instructions. - Add findNextSourceAndRewritePHI method to lookup into multiple sources returnted by the ValueTracker and rewrite PHIs with new sources. With these changes we can find more register sources and rewrite more copies to allow coaslescing of bitcast instructions. Hence, we eliminate unnecessary VR64 <-> GR64 copies in x86, but it could be extended to other archs by marking "isBitcast" on target specific instructions. The x86 example follows: A: psllq %mm1, %mm0 movd %mm0, %r9 jmp C B: por %mm1, %mm0 movd %mm0, %r9 jmp C C: movd %r9, %mm0 pshufw $238, %mm0, %mm0 Becomes: A: psllq %mm1, %mm0 jmp C B: por %mm1, %mm0 jmp C C: pshufw $238, %mm0, %mm0 Differential Revision: http://reviews.llvm.org/D11197 rdar://problem/20404526 llvm-svn: 243271
* MIR Serialization: Serialize MachineFrameInfo's callee saved information.Alex Lorenz2015-07-242-15/+60
| | | | | | | | | This commit serializes the callee saved information from the class 'MachineFrameInfo'. This commit extends the YAML mappings for the fixed and the ordinary stack objects and adds an optional 'callee-saved-register' attribute. This attribute is used to serialize the callee save information. llvm-svn: 243173
* Use make_range(rbegin(), rend()) to allow foreach loops. NFC.Pete Cooper2015-07-245-21/+14
| | | | | | | | | | | Instead of the pattern for (auto I = x.rbegin(), E = x.end(); I != E; ++I) we can use make_range to construct the reverse range and iterate using that instead. llvm-svn: 243163
* AsmPrinter: Use DICompositeType in updateAcceleratorTables(), NFCDuncan P. N. Exon Smith2015-07-241-1/+1
| | | | | | | | `DISubroutineType` is impossible at this `dyn_cast` site, since we're only dealing with named types and `DISubroutineType` cannot be named. Strengthen the `dyn_cast` to `DICompositeType`. llvm-svn: 243157
* MIR Serialization: Serialize the simple virtual register allocation hints.Alex Lorenz2015-07-242-12/+27
| | | | | | | This commit serializes the virtual register allocations hints of type 0. These hints specify the preferred physical registers for allocations. llvm-svn: 243156
* DI: Clarify isUnsignedDIType(), NFCDuncan P. N. Exon Smith2015-07-241-17/+18
| | | | | | | | | | | | Refactor `isUnsignedDIType()` to deal with `DICompositeType` explicitly. Since `DW_TAG_subroutine_type` isn't handled here (the assertions about tags rule it out), this allows strengthening the `dyn_cast` to `DIDerivedType`. Besides making the code clearer, this it removes a use of `DIDerivedTypeBase`. llvm-svn: 243148
* DI: Strengthen block-byref cast to DIDerivedType, NFCDuncan P. N. Exon Smith2015-07-241-1/+1
| | | | | | | This code is visiting the members of a block-byref, and we know those are all `DIDerivedType`. Strengthen the cast. llvm-svn: 243138
* DI: Only DICompositeType has getElements(), NFCDuncan P. N. Exon Smith2015-07-242-2/+2
| | | | | | | | There is an assertion inside `DICompositeTypeBase::getElements()` that `this` is not a `DISubroutineType`, leaving only `DICompositeType`. Make that clear at the call sites. llvm-svn: 243134
* MIR Parser: Run the machine verifier after initializing machine functions.Alex Lorenz2015-07-241-0/+4
| | | | llvm-svn: 243128
* Remove access to the DataLayout in the TargetMachineMehdi Amini2015-07-241-3/+3
| | | | | | | | | | | | | | | | | | | | | | Summary: Replace getDataLayout() with a createDataLayout() method to make explicit that it is intended to create a DataLayout only and not accessing it for other purpose. This change is the last of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: jholewinski, llvm-commits, rafael, yaron.keren Differential Revision: http://reviews.llvm.org/D11103 (cherry picked from commit 5609fc56bca971e5a7efeaa6ca4676638eaec5ea) From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 243114
* Revert "Remove access to the DataLayout in the TargetMachine"Mehdi Amini2015-07-241-3/+3
| | | | | | | | | | This reverts commit 0f720d984f419c747709462f7476dff962c0bc41. It breaks clang too badly, I need to prepare a proper patch for clang first. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 243089
* Remove access to the DataLayout in the TargetMachineMehdi Amini2015-07-241-3/+3
| | | | | | | | | | | | | | | | | | | | | | Summary: Replace getDataLayout() with a createDataLayout() method to make explicit that it is intended to create a DataLayout only and not accessing it for other purpose. This change is the last of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: jholewinski, llvm-commits, rafael, yaron.keren Differential Revision: http://reviews.llvm.org/D11103 (cherry picked from commit 5609fc56bca971e5a7efeaa6ca4676638eaec5ea) From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 243083
* MIRParser/LLVMBuild.txt: Add MC for MCRegisterInfo::getDwarfRegNum().NAKAMURA Takumi2015-07-241-1/+1
| | | | llvm-svn: 243081
* Reorder alphabetically.NAKAMURA Takumi2015-07-241-1/+1
| | | | llvm-svn: 243080
* MIR Serialization: Serialize the '.cfi_offset' CFI instruction.Alex Lorenz2015-07-234-10/+85
| | | | | Reviewers: Duncan P. N. Exon Smith llvm-svn: 243062
* fix crash in machine trace metrics due to processing dbg_value instructions ↵Sanjay Patel2015-07-231-0/+4
| | | | | | | | | | | | | | | | | | | (PR24199) The test in PR24199 ( https://llvm.org/bugs/show_bug.cgi?id=24199 ) crashes because machine trace metrics was not ignoring dbg_value instructions when calculating data dependencies. The machine-combiner pass asks machine trace metrics to calculate an instruction trace, does some reassociations, and calls MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() along with MachineTraceMetrics::invalidate(). The dbg_value instructions have their operands invalidated, but the instructions are not expected to be deleted. On a subsequent loop iteration of the machine-combiner pass, machine trace metrics would be called again and die while accessing the invalid debug instructions. Differential Revision: http://reviews.llvm.org/D11423 llvm-svn: 243057
* [PeepholeOptimizer] Refactor optimizeUncoalescable logicBruno Cardoso Lopes2015-07-221-127/+246
| | | | | | | | | | | | | | | | | | | Reapply r242294. - Create a new CopyRewriter for Uncoalescable copy-like instructions - Change the ValueTracker to return a ValueTrackerResult This makes optimizeUncoalescable looks more like optimizeCoalescable and use the CopyRewritter infrastructure. This is also the preparation for looking up into PHI nodes in the ValueTracker. rdar://problem/20404526 Differential Revision: http://reviews.llvm.org/D11195 llvm-svn: 242940
* MIR Serialization: Serialize the machine instruction's debug location.Alex Lorenz2015-07-224-2/+22
| | | | llvm-svn: 242938
* MIR Parser: Extract the MDNode parsing code into a separate method. NFC.Alex Lorenz2015-07-221-2/+11
| | | | | | | This change would allow the machine instruction parser to reuse this method when parsing the metadata node for the machine instruction's debug location property. llvm-svn: 242934
* MIR Serialization: Serialize the metadata machine operands.Alex Lorenz2015-07-224-0/+26
| | | | llvm-svn: 242916
* [PM/AA] Remove all of the dead AliasAnalysis pointers being threadedChandler Carruth2015-07-221-3/+3
| | | | | | | | | | through APIs that are no longer necessary now that the update API has been removed. This will make changes to the AA interfaces significantly less disruptive (I hope). Either way, it seems like a really nice cleanup. llvm-svn: 242882
* [BranchFolding] do not iterate the aliases of virtual registersJingyue Wu2015-07-221-15/+28
| | | | | | | | | | | | | | | | | Summary: MCRegAliasIterator only works for physical registers. So, do not run it on virtual registers. With this issue fixed, we can resurrect the BranchFolding pass in NVPTX backend. Reviewers: jholewinski, bkramer Subscribers: henryhu, meheff, llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11174 llvm-svn: 242871
* MIR Serialization: Start serializing the CFI operands with .cfi_def_cfa_offset.Alex Lorenz2015-07-214-1/+56
| | | | | | | | This commit begins serialization of the CFI index machine operands by serializing one kind of CFI instruction - the .cfi_def_cfa_offset instruction. Reviewers: Duncan P. N. Exon Smith llvm-svn: 242845
* [AsmPrinter] Check for valid constants in handleIndirectSymViaGOTPCRelBruno Cardoso Lopes2015-07-211-1/+1
| | | | | | | | | Check whether BaseCst is valid before extracting a GlobalValue. This fixes PR24163. Patch by David Majnemer. llvm-svn: 242840
* MIR Parser: Reuse the function 'lexName' when lexing global value tokens. NFC.Alex Lorenz2015-07-211-31/+19
| | | | | | | This commit refactors the function 'maybeLexGlobalValue' so that now it reuses the function 'lexName' when lexing a named global value token. llvm-svn: 242837
* MIR Serialization: Serialize the external symbol machine operands.Alex Lorenz2015-07-215-1/+65
| | | | | Reviewers: Duncan P. N. Exon Smith llvm-svn: 242806
* Targets: commonize some stack realignment codeJF Bastien2015-07-201-1/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does the following: * Fix FIXME on `needsStackRealignment`: it is now shared between multiple targets, implemented in `TargetRegisterInfo`, and isn't `virtual` anymore. This will break out-of-tree targets, silently if they used `virtual` and with a build error if they used `override`. * Factor out `canRealignStack` as a `virtual` function on `TargetRegisterInfo`, by default only looks for the `no-realign-stack` function attribute. Multiple targets duplicated the same `needsStackRealignment` code: - Aarch64. - ARM. - Mips almost: had extra `DEBUG` diagnostic, which the default implementation now has. - PowerPC. - WebAssembly. - x86 almost: has an extra `-force-align-stack` option, which the default implementation now has. The default implementation of `needsStackRealignment` used to just return `false`. My current patch changes the behavior by simply using the above shared behavior. This affects: - AMDGPU - BPF - CppBackend - MSP430 - NVPTX - Sparc - SystemZ - XCore - Out-of-tree targets This is a breaking change! `make check` passes. The only implementation of the `virtual` function (besides the slight different in x86) was Hexagon (which did `MF.getFrameInfo()->getMaxAlignment() > 8`), and potentially some out-of-tree targets. Hexagon now uses the default implementation. `needsStackRealignment` was being overwritten in `<Target>GenRegisterInfo.inc`, to return `false` as the default also did. That was odd and is now gone. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11160 llvm-svn: 242727
* MachineScheduler: Restrict macroop fusion to data-dependent instructions.Matthias Braun2015-07-201-9/+33
| | | | | | | | | | | | | | Before creating a schedule edge to encourage MacroOpFusion check that: - The predecessor actually writes a register that the branch reads. - The predecessor has no successors in the ScheduleDAG so we can schedule it in front of the branch. This avoids skewing the scheduling heuristic in cases where macroop fusion cannot happen. Differential Revision: http://reviews.llvm.org/D10745 llvm-svn: 242723
* MIR Serialization: Initial serialization of machine constant pools.Alex Lorenz2015-07-206-1/+89
| | | | | | | | | | This commit implements the initial serialization of machine constant pools and the constant pool index machine operands. The constant pool is serialized using a YAML sequence of YAML mappings that represent the constant values. The target-specific constant pool items aren't serialized by this commit. Reviewers: Duncan P. N. Exon Smith llvm-svn: 242707
* [ImplicitNullChecks] Work with implicit defs.Sanjoy Das2015-07-201-6/+11
| | | | | | | | | | | | | | | Summary: This change generalizes the implicit null checks pass to work with instructions that don't have any explicit register defs. This lets us use X86's `cmp` against memory as faulting load instructions. Reviewers: reames, JosephTremoulet Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11286 llvm-svn: 242703
* MIR Parser: Add support for quoted named global value operands.Alex Lorenz2015-07-203-7/+102
| | | | | | | | | | This commit extends the machine instruction lexer and implements support for the quoted global value tokens. With this change the syntax for the global value identifier tokens becomes identical to the syntax for the global identifier tokens from the LLVM's assembly language. Reviewers: Duncan P. N. Exon Smith llvm-svn: 242702
* [DAGCombiner] Fixed minor typo that was missed in D9097.Simon Pilgrim2015-07-191-2/+2
| | | | | | We don't bitcast the UNDEFs - that is done in visitVECTOR_SHUFFLE, and the getValueType should come from the operand's SDValue not the SDNode. llvm-svn: 242640
* Remove TargetInstrInfo::canFoldMemoryOperandSimon Pilgrim2015-07-191-5/+0
| | | | | | | | | | canFoldMemoryOperand is not actually used anywhere in the codebase - all existing users instead call foldMemoryOperand directly when they wish to fold and can correctly deduce what they need from the return value. This patch removes the canFoldMemoryOperand base function and the target implementations; only x86 had a real (bit-rotted) implementation, although AMDGPU had a preparatory stub that had never needed to be completed. Differential Revision: http://reviews.llvm.org/D11331 llvm-svn: 242638
* Use SDValue bool check. NFCI.Simon Pilgrim2015-07-191-58/+39
| | | | llvm-svn: 242636
* [AggressiveAntiDepBreaker] Use range loops for multimap access.Benjamin Kramer2015-07-181-23/+8
| | | | | | No functionality change intended. llvm-svn: 242620
* [RAGreedy] Add an experimental deferred spilling feature.Quentin Colombet2015-07-171-6/+37
| | | | | | | | | | | | | | | | The idea of deferred spilling is to delay the insertion of spill code until the very end of the allocation. A "candidate" to spill variable might not required to be spilled because of other evictions that happened after this decision was taken. The spirit is similar to the optimistic coloring strategy implemented in Preston and Briggs graph coloring algorithm. For now, this feature is highly experimental. Although correct, it would require much more modification to properly model the effect of spilling. Anyway, this early patch helps prototyping this feature. Note: The test case cannot unfortunately be reduced and is probably fragile. llvm-svn: 242585
* MIR Parser: Allow the dollar characters in all of the identifier tokens.Alex Lorenz2015-07-171-1/+4
| | | | | | | | | | This commit modifies the machine instruction lexer so that it now accepts the '$' characters in identifier tokens. This change makes the syntax for unquoted global value tokens consistent with the syntax for the global idenfitier tokens in the LLVM's assembly language. llvm-svn: 242584
* Use llvm_unreachable() instead of report_fatal_error() if the machine model ↵Matthias Braun2015-07-171-5/+3
| | | | | | | | | is incomplete This error is for developers only so it makes sense to abort and get a backtrace. llvm-svn: 242551
* Make global aliases have symbol size equal to their typeJohn Brawn2015-07-171-0/+10
| | | | | | | | | | This is mainly for the benefit of GlobalMerge, so that an alias into a MergedGlobals variable has the same size as the original non-merged variable. Differential Revision: http://reviews.llvm.org/D10837 llvm-svn: 242520
* Only do fmul (fadd x, x), c combine if the fadd only has one useMatt Arsenault2015-07-171-1/+3
| | | | | | This was increasing the instruction count if the fadd has multiple uses. llvm-svn: 242498
OpenPOWER on IntegriCloud