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* Debug info: Don't emit a DW_AT_byte_size when emitting a DWARF4 bit field.Adrian Prantl2016-05-161-1/+2
| | | | | | | | | | The DWARF spec clearly states that a bit field member should have either a DW_AT_byte_size or a DW_AT_bit_size, but not both. Also the DW_AT_byte_size is redundant with the size of the type of the member. This fixes a bug found in PR 27758. llvm-svn: 269714
* Fail early on unknown appending linkage variables.Rafael Espindola2016-05-161-6/+3
| | | | | | | | | | | | | In practice only a few well known appending linkage variables work. Currently if codegen sees an unknown appending linkage variable it will just print it as a regular global. That is wrong as the symbol in the produced object file has different semantics as the one provided by the appending linkage. This just errors early instead of producing a broken .o. llvm-svn: 269706
* SelectionDAG: Select min/max when both are usedMatt Arsenault2016-05-161-1/+9
| | | | | | | | | | | Allow two users of the condition if the other user is also a min/max select. i.e. %c = icmp slt i32 %x, %y %min = select i1 %c, i32 %x, i32 %y %max = select i1 %c, i32 %y, i32 %x llvm-svn: 269699
* Remove extra whitespace. NFC.Chad Rosier2016-05-161-1/+1
| | | | llvm-svn: 269685
* [codeview] Align class and print names of typesReid Kleckner2016-05-131-1/+1
| | | | | | | | | | | | Summary: This way we can get rid of one of the fields in the .def file. Reviewers: llvm-commits Subscribers: zturner Differential Revision: http://reviews.llvm.org/D20251 llvm-svn: 269461
* Rename getLargestLegalIntTypeSize to getLargestLegalIntTypeSizeInBits(). NFC.Jun Bum Lim2016-05-132-2/+2
| | | | | | | | | | | | Summary: Rename DataLayout::getLargestLegalIntTypeSize to DataLayout::getLargestLegalIntTypeSizeInBits() to prevent similar mistakes fixed in r269433. Reviewers: joker.eph, mcrosier Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D20248 llvm-svn: 269456
* Revert "LiveIntervalAnalysis: Rework constructMainRangeFromSubranges()"Tom Stellard2016-05-124-48/+246
| | | | | | | | This reverts commit r269016 and also the follow-up commit r269020. This patch caused PR27705. llvm-svn: 269344
* Fix option description /NFCXinliang David Li2016-05-121-2/+2
| | | | llvm-svn: 269307
* [SelectionDAG] Attempt to split BITREVERSE vector legalization into BSWAP ↵Simon Pilgrim2016-05-121-5/+32
| | | | | | | | | | | | | | and BITREVERSE stages For BITREVERSE, bit shifting/masking every bit in a vector element is a very lengthy procedure. If the input vector type is a whole multiple of bytes wide then we can split this into a BSWAP shuffle stage (to reverse at the byte level) and then a BITREVERSE stage applied to each byte. Most vector capable targets can efficiently BSWAP using shuffles resulting in a considerable reduction in instructions. With this patch targets would only need to implement a target specific vXi8 BITREVERSE implementation to efficiently reverse most legal vector types. Differential Revision: http://reviews.llvm.org/D19978 llvm-svn: 269290
* [Layout] Add a new option (NFC)Xinliang David Li2016-05-121-1/+7
| | | | | | | | | | Currently cost based loop rotation algo can only be turned on with two conditions: the function has real profile data, and -precise-rotation-cost flag is turned on. This is not convenient for developers to experiment when profile is not available. Add a new option to force the new rotation algorithm -force-precise-rotation-cost llvm-svn: 269266
* Fix a bug when hoist spill to a BB with landingpad successor.Wei Mi2016-05-111-6/+10
| | | | | | | | | | | | | | | This is to fix the bug in https://llvm.org/bugs/show_bug.cgi?id=27612. When spill is hoisted to a BB with landingpad successor, and if the VNI of the spill reg lives into the landingpad successor, the spill should be inserted before the call which may throw exception. InsertPointAnalysis is used to compute the safe insert point. http://reviews.llvm.org/D20027 is a preparing patch for this patch. Differential Revision: http://reviews.llvm.org/D19884. llvm-svn: 269249
* [NFC] Extract LastSplitPoint computation from SplitAnalysis to a new classWei Mi2016-05-112-64/+101
| | | | | | | | | | | | InsertPointAnalysis. Because both split and spill hoisting want to use LastSplitPoint computation result, extract the LastSplitPoint computation from SplitAnalysis class which also contains a bunch of other analysises only related to split. Differential Revision: http://reviews.llvm.org/D20027. llvm-svn: 269248
* MachineVerifier: Fix error reporting.Matthias Braun2016-05-111-4/+10
| | | | | | | Do not use getVRegDef() to print "the definition" of a vreg. If there are multiple or none the function will fail. llvm-svn: 269239
* SDAG: Have SelectNodeTo replace uses if it CSE's instead of morphing a nodeJustin Bogner2016-05-112-9/+8
| | | | | | | | It's awkward to force callers of SelectNodeTo to figure out whether the node was morphed or CSE'd. Update uses here instead of requiring callers to (sometimes) do it. llvm-svn: 269235
* Return a StringRef from getSection.Rafael Espindola2016-05-111-1/+1
| | | | | | This is similar to how getName is handled. llvm-svn: 269218
* Refactor CodeView type records to use common code.Zachary Turner2016-05-111-2/+2
| | | | | | | Differential Revision: http://reviews.llvm.org/D20138 Reviewed By: rnk llvm-svn: 269216
* fix typos in comments; NFCSanjay Patel2016-05-111-41/+40
| | | | llvm-svn: 269206
* Merge two unreachable cases.Rafael Espindola2016-05-111-2/+1
| | | | llvm-svn: 269189
* SDAG: Make SelectCodeCommon return voidJustin Bogner2016-05-101-25/+41
| | | | | | | | | | | This means SelectCode unconditionally returns nullptr now. I'll follow up with a change to make that return void as well, but it seems best to keep that one very mechanical. This is part of the work to have Select return void instead of an SDNode *, which is in turn part of llvm.org/pr26808. llvm-svn: 269136
* ScheduleDAGInstrs: Comment on why subreg defs are not seen as uses; NFCMatthias Braun2016-05-101-0/+4
| | | | | | | | Usually subregister definitions are consider uses of the remaining lanes that did not get defined. Add a comment why the code in ScheduleDAGInstrs does not add use dependencies regardless. llvm-svn: 269107
* Debug Info: Prevent DW_AT_abstract_origin from being emitted twiceAdrian Prantl2016-05-101-7/+0
| | | | | | | | | | | | for the same subprogram. This fixes a bug where DW_AT_abstract_origin is being emitted twice for the same subprogram if a function is both inlined and emitted in the same translation unit, by restoring the pre-r266446 behavior. http://reviews.llvm.org/D20072 llvm-svn: 269103
* Fix PR26655: Bail out if all regs of an inst BUNDLE have the correct kill flagMandeep Singh Grang2016-05-102-27/+18
| | | | | | | | | | | | | | | | | | | | Summary: While setting kill flags on instructions inside a BUNDLE, we bail out as soon as we set kill flag on a register. But we are missing a check when all the registers already have the correct kill flag set. We need to bail out in that case as well. This patch refactors the old code and simply makes use of the addRegisterKilled function in MachineInstr.cpp in order to determine whether to set/remove kill on an instruction. Reviewers: apazos, t.p.northover, pete, MatzeB Subscribers: MatzeB, davide, llvm-commits Differential Revision: http://reviews.llvm.org/D17356 llvm-svn: 269092
* [ScheduleDAG] Make sure to process all def operands before any use operandsKrzysztof Parzyszek2016-05-101-8/+25
| | | | | | | | | | | | | | | | | An example from Hexagon where things went wrong: %R0<def> = L2_loadrigp <ga:@fp04> ; load function address J2_callr %R0<kill>, ..., %R0<imp-def> ; call *R0, return value in R0 ScheduleDAGInstrs::buildSchedGraph would visit all instructions going backwards, and in each instruction it would visit all operands in their order on the operand list. In the case of this call, it visited the use of R0 first, then removed it from the set Uses after it visited the def. This caused the DAG to be missing the data dependence edge on R0 between the load and the call. Differential Revision: http://reviews.llvm.org/D20102 llvm-svn: 269076
* [PR27599] [SystemZ] [SelectionDAG] Fix extension of atomic cmpxchg result.Marcin Koscielnicki2016-05-101-4/+17
| | | | | | | | | | | | Currently, SelectionDAG assumes 8/16-bit cmpxchg returns either a sign extended result, or a zero extended result. SystemZ takes a third option by returning junk in the high bits (rotated contents of the other bytes in the memory word). In that case, don't use Assert*ext, and zero-extend the result ourselves if a comparison is needed. Differential Revision: http://reviews.llvm.org/D19800 llvm-svn: 269075
* [foldMemoryOperand()] Pass LiveIntervals to enable liveness check.Jonas Paulsson2016-05-103-7/+9
| | | | | | | | | | | | | | | SystemZ (and probably other targets as well) can fold a memory operand by changing the opcode into a new instruction that as a side-effect also clobbers the CC-reg. In order to do this, liveness of that reg must first be checked. When LIS is passed, getRegUnit() can be called on it and the right LiveRange is computed on demand. Reviewed by Matthias Braun. http://reviews.llvm.org/D19861 llvm-svn: 269026
* LiveIntervalAnalysis: Rework constructMainRangeFromSubranges()Matthias Braun2016-05-104-246/+48
| | | | | | | | | | | | | | | | | | We now use LiveRangeCalc::extendToUses() instead of a specially designed algorithm in constructMainRangeFromSubranges(): - The original motivation for constructMainRangeFromSubranges() were differences between the main liverange and subranges because of hidden dead definitions. This case however cannot happen anymore with the DetectDeadLaneMasks pass in place. - It simplifies the code. - This fixes a longstanding bug where we did not properly create new SSA values on merging control flow (the MachineVerifier missed most of these cases). - Move constructMainRangeFromSubranges() to LiveIntervalAnalysis and LiveRangeCalc to better match the implementation/available helper functions. llvm-svn: 269016
* LiveInterval: Avoid unnecessary auto, add const; NFCMatthias Braun2016-05-101-3/+3
| | | | llvm-svn: 269015
* TargetPassConfig: Set PrintMachineCode even if addMachinePasses() does not run.Matthias Braun2016-05-101-5/+5
| | | | llvm-svn: 269013
* [WebAssembly] Move register stackification and coloring to a late phase.Dan Gohman2016-05-101-1/+1
| | | | | | | | | | | | | | | | | | | Move the register stackification and coloring passes to run very late, after PEI, tail duplication, and most other passes. This means that all code emitted and expanded by those passes is now exposed to these passes. This also eliminates the need for prologue/epilogue code to be manually stackified, which significantly simplifies the code. This does require running LiveIntervals a second time. It's useful to think of these late passes not as late optimization passes, but as a domain-specific compression algorithm based on knowledge of liveness information. It's used to compress the code after all conventional optimizations are complete, which is why it uses LiveIntervals at a phase when actual optimization passes don't typically need it. Differential Revision: http://reviews.llvm.org/D20075 llvm-svn: 269012
* CodeGen: Move TargetPassConfig from Passes.h to an own header; NFCMatthias Braun2016-05-106-3/+13
| | | | | | | | Many files include Passes.h but only a fraction needs to know about the TargetPassConfig class. Move it into an own header. Also rename Passes.cpp to TargetPassConfig.cpp while we are at it. llvm-svn: 269011
* PrologEpilogInserter: Remove unnecessary dependencyMatthias Braun2016-05-101-2/+0
| | | | llvm-svn: 269010
* LLVMTargetMachine: Add functions to create MIModuleInfo/MIFunction; NFCMatthias Braun2016-05-101-9/+17
| | | | | | | | | | | Add convenience function to create MachineModuleInfo and MachineFunctionAnalysis passes and add them to a pass manager. Despite factoring out some shared code in LiveIntervalTest/LLVMTargetMachine this will be used by my upcoming llc change. llvm-svn: 269002
* [CGP] avoid crashing from weightlessnessSanjay Patel2016-05-091-3/+5
| | | | | | | It's possible that we have branch weights with 0 values. In that case, don't try to create an impossible BranchProbability. llvm-svn: 268935
* [TargetLowering] make helper function for SetCC + and optimizations (NFC)Sanjay Patel2016-05-091-52/+40
| | | | | | | | | | After looking at D19087 again, it occurred to me that we can do better. If we consolidate the valueHasExactlyOneBitSet() transforms, we won't incur extra overhead from calling it a 2nd time, and we can shrink SimplifySetCC() a bit. No functional change intended. Differential Revision: http://reviews.llvm.org/D20050 llvm-svn: 268932
* Fix unused variable warning.Simon Pilgrim2016-05-071-1/+0
| | | | llvm-svn: 268867
* [SelectionDAG] Added bitreverse(bitreverse(v)) --> vSimon Pilgrim2016-05-072-0/+18
| | | | | | Added bitreverse creation testing llvm-svn: 268865
* [x86, BMI] add TLI hook for 'andn' and use it to simplify comparisonsSanjay Patel2016-05-071-0/+49
| | | | | | | | | | | | | | | | | | | | | For the sake of minimalism, this patch is x86 only, but I think that at least PPC, ARM, AArch64, and Sparc probably want to do this too. We might want to generalize the hook and pattern recognition for a target like PPC that has a full assortment of negated logic ops (orc, nand). Note that http://reviews.llvm.org/D18842 will cause this transform to trigger more often. For reference, this relates to: https://llvm.org/bugs/show_bug.cgi?id=27105 https://llvm.org/bugs/show_bug.cgi?id=27202 https://llvm.org/bugs/show_bug.cgi?id=27203 https://llvm.org/bugs/show_bug.cgi?id=27328 Differential Revision: http://reviews.llvm.org/D19087 llvm-svn: 268858
* DetectDeadLanes: Increase precision when detecting undef inputsMatthias Braun2016-05-061-53/+121
| | | | | | | | | | | | | In case of COPY-like instruction we may be able to deduce that a certain input is unused, based on the used lanes of the register defined by the instruction. This even works accross otherwise incompatible copies (no need to have compatible lanemasks, completely unused operands are still completely unused). It even makes sense to redo the analysis in this case since we gained information for a case we previously stopped at because of the incompatible masks. llvm-svn: 268815
* DetectDeadLanes: Cleanup, assert on some impossible cases.Matthias Braun2016-05-061-9/+8
| | | | llvm-svn: 268814
* LiveIntervalAnalysis: Fix handleMove() extending liverange for undef inputsMatthias Braun2016-05-061-3/+6
| | | | | | | Fix handleMove() incorrectly extending liveranges when an undef input of a vreg was moved past the (current) end of the liverange. llvm-svn: 268805
* SDAG: Don't leave dangling dead nodes after SelectCodeCommonJustin Bogner2016-05-061-1/+3
| | | | | | | Relying on the caller to clean up after we've replaced all uses of a node won't work when we've migrated to the `void Select(...)` API. llvm-svn: 268774
* [CodeGen] Round [SU]INT_TO_FP result when promoting from f16.Ahmed Bougacha2016-05-061-1/+6
| | | | | | | | | | | | If we don't, values that aren't precisely representable in f16 could be used as-is in a promoted f32 operation, which would produce incorrect results. AArch64 had the correct behavior; add a focused test. Fixes http://llvm.org/PR26871 llvm-svn: 268700
* SDAG: Rename Select->SelectImpl and repurpose Select as returning voidJustin Bogner2016-05-051-17/+1
| | | | | | | | | | | | | | This is a step towards removing the rampant undefined behaviour in SelectionDAG, which is a part of llvm.org/PR26808. We rename SelectionDAGISel::Select to SelectImpl and update targets to match, and then change Select to return void and consolidate the sketchy behaviour we're trying to get away from there. Next, we'll update backends to implement `void Select(...)` instead of SelectImpl and eventually drop the base Select implementation. llvm-svn: 268693
* SDAG: Remove OPC_MarkGlueResults and associated logic. NFCJustin Bogner2016-05-051-60/+19
| | | | | | | | | This opcode never happens in practice, and yet the logic we have in place to handle it would be undefined behaviour if we ever executed it. Remove it rather than trying to refactor code that's never reached. llvm-svn: 268692
* MachineFunction: Add a const modifier to print() parameterMatthias Braun2016-05-052-3/+4
| | | | llvm-svn: 268657
* clean up; NFCISanjay Patel2016-05-041-15/+15
| | | | llvm-svn: 268564
* [SelectionDAG] BITREVERSE vector legalization of bit operations (REAPPLIED)Simon Pilgrim2016-05-041-2/+2
| | | | | | | | Some vector bit operations are promoted instead of having custom lowering. This patch changes the isOperationLegalOrCustom tests for vector AND/OR operations to use a new TLI helper isOperationLegalOrCustomOrPromote instead, allowing the SSE implementations to stay on the simd unit. Differential Revision: http://reviews.llvm.org/D19805 llvm-svn: 268561
* Spelling and grammar corrections in comments.Eric Christopher2016-05-042-16/+16
| | | | llvm-svn: 268560
* Revert r268504Simon Pilgrim2016-05-041-2/+2
| | | | llvm-svn: 268526
* [SelectionDAG] BITREVERSE vector legalization of bit operationsSimon Pilgrim2016-05-041-2/+2
| | | | | | | | Vector bit operations are typically promoted instead of having custom lowering. This patch changes the isOperationLegalOrCustom tests for vector AND/OR operations to use isOperationLegalOrPromote instead, allowing the SSE implementations to stay on the simd unit. Differential Revision: http://reviews.llvm.org/D19805 llvm-svn: 268504
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