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* Fix the failure caused by r322773Volkan Keles2018-01-181-8/+3
| | | | | | Do not run GlobalISel if `-fast-isel=0 -global-isel=false`. llvm-svn: 322800
* [MachineOutliner] Add DISubprograms to outlined functions.Jessica Paquette2018-01-181-2/+47
| | | | | | | | | | Before, it wasn't possible to get backtraces inside outlined functions. This commit adds DISubprograms to the IR functions created by the outliner which makes this possible. Also attached a test that ensures that the produced debug information is correct. This is useful to users that want to debug outlined code. llvm-svn: 322789
* [CodeGen] Hoist common AsmPrinter code out of X86, ARM, and AArch64Reid Kleckner2018-01-171-0/+16
| | | | | | | | | | | Every known PE COFF target emits /EXPORT: linker flags into a .drective section. The AsmPrinter should handle this. While we're at it, use global_values() and emit each export flag with its own .ascii directive. This should make the .s file output more readable. llvm-svn: 322788
* Add a TargetOption to enable/disable GlobalISelVolkan Keles2018-01-171-15/+14
| | | | | | | | | | | | | | | | | | | | | Summary: This patch adds a new target option in order to control GlobalISel. This will allow the users to enable/disable GlobalISel prior to the backend by calling `TargetMachine::setGlobalISel(bool Enable)`. No test case as there is already a test to check GlobalISel command line options. See: CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll. Reviewers: qcolombet, aemerson, ab, dsanders Reviewed By: qcolombet Subscribers: rovka, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D42137 llvm-svn: 322773
* Add support for emitting libcalls for x86_fp80 -> fp128 and vice-versaBenjamin Kramer2018-01-171-0/+6
| | | | | | compiler_rt doesn't provide them (yet), but libgcc does. PR34076. llvm-svn: 322772
* [LegalizeDAG] Fix ATOMIC_CMP_SWAP_WITH_SUCCESS legalization.Eli Friedman2018-01-171-2/+2
| | | | | | | | | | | | | The code wasn't zero-extending correctly, so the comparison could spuriously fail. Adds some AArch64 tests to cover this case. Inspired by D41791. Differential Revision: https://reviews.llvm.org/D41798 llvm-svn: 322767
* [GISel] Make constrainSelectedInstRegOperands() available to the legalizer. NFCAditya Nandakumar2018-01-172-44/+45
| | | | | | https://reviews.llvm.org/D42149 llvm-svn: 322743
* [ARM GlobalISel] Legalize G_FPEXT and G_FPTRUNCDiana Picus2018-01-171-0/+47
| | | | | | | | | | | Mark G_FPEXT and G_FPTRUNC as legal or libcall, depending on hardware support, but only for conversions between float and double. Also add the necessary boilerplate so that the LegalizerHelper can introduce the required libcalls. This also works only for float and double, but isn't too difficult to extend when the need arises. llvm-svn: 322651
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-01-174-7/+7
| | | | | | "the the" -> "the" llvm-svn: 322636
* Don't emit apple accelerator tables on non-darwin targetsPavel Labath2018-01-171-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Currently -glldb turns on emission of apple tables on all targets, but lldb is only really capable of consuming them on darwin. Furthermore, making lldb consume these tables is not straight-forward because of the differences in how the debug info is distributed on darwin vs. elf targets. The darwin debug model assumes that the debug info (along with accelerator tables) will either remain in the .o files or it will be linked into a dsym bundle by a linker that knows how to merge these tables. In the elf world, all present linkers will simply concatenate these accelerator tables into the shared object. Since the tables are not self-terminating, this renders the tables unusable, as the debugger cannot pry the individual tables apart anymore. It might theoretically be possible to make the tables work with split dwarf, as that is somewhat similar to the apple .o model, but unfortunately right now the combination of -glldb and -gsplit-dwarf produces broken object files. Until these issues are resolved there is no point in emitting the apple tables for these targets. At best, it wastes space; at worst, it breaks compilation and prevents the user from getting other benefits of -glldb. Reviewers: probinson, aprantl, dblaikie Subscribers: emaste, dim, llvm-commits, JDevlieghere Differential Revision: https://reviews.llvm.org/D41986 llvm-svn: 322633
* [MC] Fix -stack-size-section on ARMSean Eveson2018-01-171-2/+1
| | | | | | | | Change symbol values in the stack_size section from being 8 bytes, to being a target dependent size. Differential Revision: https://reviews.llvm.org/D42108 llvm-svn: 322619
* [CodeGen] Skip some instructions that shouldn't affect shrink-wrappingFrancis Visoiu Mistrih2018-01-161-5/+5
| | | | | | | | | | | r320606 checked for MI.isMetaInstruction which skips all DBG_VALUEs. This also skips IMPLICIT_DEFs and other instructions that may def / read a register. Differential Revision: https://reviews.llvm.org/D42119 llvm-svn: 322584
* [LiveDebugValues] recognize spilled reg killed in instruction after spillPetar Jovanovic2018-01-161-7/+30
| | | | | | | | | | | Current condition for spill instruction recognition in LiveDebugValues does not recognize case when register is spilled and killed in next instruction. Patch by Nikola Prica. Differential Revision: https://reviews.llvm.org/D41226 llvm-svn: 322554
* [CodeGen] Remove special case of printing subRegIdx from MachineInstr::printFrancis Visoiu Mistrih2018-01-161-3/+0
| | | | | | | Support in MachineOperand has been added in r320209. No need to special case this anymore. llvm-svn: 322542
* [CodeGen][NFC] Correct case for printSubRegIdxFrancis Visoiu Mistrih2018-01-163-3/+3
| | | | llvm-svn: 322541
* Revert "[DAG] Elide overlapping stores"Benjamin Kramer2018-01-151-20/+21
| | | | | | | This reverts commit r322085. Internal PPC testing is still showing the same symptoms as when this patch landed the last time. llvm-svn: 322474
* [MachineOutliner] Move hasAddressTaken check to MachineOutliner.cppJessica Paquette2018-01-131-2/+2
| | | | | | | | | | | | | *Mostly* NFC. Still updating the test though just for completeness. This moves the hasAddressTaken check to MachineOutliner.cpp and replaces it with a per-basic block test rather than a per-function test. The old test was too conservative and was preventing functions in C programs from being outlined even though they were safe to outline. This was mostly a problem in C sources. llvm-svn: 322425
* [NFC] Change MemIntrinsicInst::setAlignment() to take an unsigned instead of ↵Daniel Neilson2018-01-122-7/+10
| | | | | | | | | | | a Constant Summary: In preparation for https://reviews.llvm.org/D41675 this NFC changes this prototype of MemIntrinsicInst::setAlignment() to accept an unsigned instead of a Constant. llvm-svn: 322403
* [DWARFv5] CodeGen support for MD5 file checksumsPaul Robinson2018-01-125-45/+48
| | | | | | | | | | Pass MD5 checksums through from IR to assembly/object files. After this, getting Clang to compute the MD5 should be the last step to supporting MD5 in the DWARF v5 line table header. Differential Revision: https://reviews.llvm.org/D41926 llvm-svn: 322391
* [ARM GlobalISel] Legalize G_FMADiana Picus2018-01-121-2/+9
| | | | | | | | | | | For hard float with VFP4, it is legal. Otherwise, we use libcalls. This needs a bit of support in the LegalizerHelper for soft float because we didn't handle G_FMA libcalls yet. The support is trivial, as the only difference between G_FMA and other libcalls that we already handle is that it has 3 input operands rather than just 2. llvm-svn: 322366
* [CGP] Re-enable Select in complex addressing modeSerguei Katkov2018-01-121-1/+1
| | | | | | | | Re-enable Select after a couple of fixes. Differential Revision: https://reviews.llvm.org/D40634 llvm-svn: 322358
* PeepholeOpt cleanup/refactor; NFCMatthias Braun2018-01-111-440/+370
| | | | | | | | | | | | | | | | | | - Less unnecessary use of `auto` - Add early `using RegSubRegPair(AndIdx) =` to avoid countless `TargetInstrInfo::` qualifications. - Use references instead of pointers where possible. - Remove unused parameters. - Rewrite the CopyRewriter class hierarchy: - Pull out uncoalescable copy rewriting functionality into PeepholeOptimizer class. - Use an abstract base class to make it clear that rewriters are independent. - Remove unnecessary \brief in doxygen comments. - Remove unused constructor and method from ValueTracker. - Replace UseAdvancedTracking of ValueTracker with DisableAdvCopyOpt use. llvm-svn: 322325
* PeepholeOptimizer: Fix for vregs without defsMatthias Braun2018-01-112-3/+22
| | | | | | | | | | The PeepholeOptimizer would fail for vregs without a definition. If this was caused by an undef operand abort to keep the code simple (so we don't need to add logic everywhere to replicate the undef flag). Differential Revision: https://reviews.llvm.org/D40763 llvm-svn: 322319
* PeepholeOptimizer: Do not form PHI with subreg argumentsMatthias Braun2018-01-111-22/+19
| | | | | | | | | | | | | | | | | | | | | When replacing a PHI the PeepholeOptimizer currently takes the register class of the register at the first operand. This however is not correct if this argument has a subregister index. As there is currently no API to query the register class resulting from applying a subregister index to all registers in a class, we can only abort in these cases and not perform the transformation. This changes findNextSource() to require the end of all copy chains to not use a subregister if there is any PHI in the chain. I had to rewrite the overly complicated inner loop there to have a good place to insert the new check. This fixes https://llvm.org/PR33071 (aka rdar://32262041) Differential Revision: https://reviews.llvm.org/D40758 llvm-svn: 322313
* dag-combine: Transfer debug information when folding (zext (truncate x))Adrian Prantl2018-01-111-1/+4
| | | | | | | | | | | -> (zext (truncate x)) This patch adds debug info support to the dagcombine rule (zext (truncate x)) -> (zext (truncate x)). Differential Revision: https://reviews.llvm.org/D41924 llvm-svn: 322304
* DAGCombine: Let truncates negate extension through extract-subvectorZvi Rackover2018-01-111-0/+16
| | | | | | | | | | | | | | | | | | | | | | Summary: Fold cases such as: (v8i8 truncate (v8i32 extract_subvector (v16i32 sext (v16i8 V), Idx))) -> (v8i8 extract_subvector (v16i8 V), Idx) This can be generalized to cases where the truncate and extend do not fully cancel each other out, but it may require querying the target about profitability. Reviewers: RKSimon, craig.topper, spatel, efriedma Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41927 llvm-svn: 322300
* [VectorLegalizer] Remove broken code in ExpandStore.Jonas Paulsson2018-01-111-28/+0
| | | | | | | | | | | | | | The code that is supposed to "Round odd types to the next pow of two" seems broken and as well completely unused (untested). It also seems that ExpandStore really shouldn't ever change the memory VT, which this in fact does. As a first step in fixing the broken handling of vector stores (of irregular types, e.g. an i1 vector), this code is removed. For discussion, see https://bugs.llvm.org/show_bug.cgi?id=35520. Review: Eli Friedman llvm-svn: 322275
* [CodeView] Fix the type for a variadic argumentAaron Smith2018-01-111-0/+12
| | | | | | | | | | | | | | Summary: - MSVC uses the none type for a variadic argument in CodeView - Add a unit test Reviewers: zturner, llvm-commits Reviewed By: zturner Differential Revision: https://reviews.llvm.org/D41931 llvm-svn: 322257
* [DWARF][NFC] Overload AsmPrinter::emitDwarfStringOffsets() to take a ↵Wolfgang Pieb2018-01-111-3/+4
| | | | | | | | | | DwarfStringPoolEntry record. Differential Revision: https://reviews.llvm.org/D41920 llvm-svn: 322250
* Revert "AArch64: Fix emergency spillslot being out of reach for large ↵Matthias Braun2018-01-102-5/+0
| | | | | | | | | | | | callframes" Revert for now as the testcase is hitting a pre-existing verifier error that manifest as a failure when expensive checks are enabled (or -verify-machineinstrs) is used. This reverts commit r322200. llvm-svn: 322231
* LiveRangeEdit: Inline markDeadRemat() into only user; NFCMatthias Braun2018-01-101-1/+1
| | | | | | | This function was only called from a single place in which we didn't even need the `if (DeadRemats)` check. llvm-svn: 322230
* LiveRangeEdit: Simplify code; NFCMatthias Braun2018-01-101-12/+14
| | | | | | | | Simplify the code slightly: Instead of creating empty subranges in one case and immediately removing them, do not create them in the first place. llvm-svn: 322226
* TargetLoweringBase: The ios simulator has no bzero function.Matthias Braun2018-01-101-3/+12
| | | | | | | | Make sure I really get back to the beahvior before my rewrite in r321035 which turned out not to be completely NFC as I changed the behavior for the ios simulator environment. llvm-svn: 322223
* [SelectionDAG][X86] Explicitly store the scale in the gather/scatter ISD nodesCraig Topper2018-01-105-24/+46
| | | | | | | | | | Currently we infer the scale at isel time by analyzing whether the base is a constant 0 or not. If it is we assume scale is 1, else we take it from the element size of the pass thru or stored value. This seems a little weird and I think it makes more sense to make it explicit in the DAG rather than doing tricky things in the backend. Most of this patch is just making sure we copy the scale around everywhere. Differential Revision: https://reviews.llvm.org/D40055 llvm-svn: 322210
* AArch64: Fix emergency spillslot being out of reach for large callframesMatthias Braun2018-01-102-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Large callframes (calls with several hundreds or thousands or parameters) could lead to situations in which the emergency spillslot is out of range to be addressed relative to the stack pointer. This commit forces the use of a frame pointer in the presence of large callframes. This commit does several things: - Compute max callframe size at the end of instruction selection. - Add mirFileLoaded target callback. Use it to compute the max callframe size after loading a .mir file when the size wasn't specified in the file. - Let TargetFrameLowering::hasFP() return true if there exists a callframe > 255 bytes. - Always place the emergency spillslot close to FP if we have a frame pointer. - Note that `useFPForScavengingIndex()` would previously return false when a base pointer was available leading to the emergency spillslot getting allocated late (that's the whole effect of this callback). Which made no sense to me so I took this case out: Even though the emergency spillslot is technically not referenced by FP in this case we still want it allocated early. Differential Revision: https://reviews.llvm.org/D40876 llvm-svn: 322200
* [SelectionDAGBuilder] Chain prefetches less aggressively.Jonas Paulsson2018-01-101-7/+13
| | | | | | | | | | | | | Prefetches used to always be chained between any previous and following memory accesses. The problem with this was that later optimizations, such as folding of a load into the user instruction, got disrupted. This patch relaxes the chaining of prefetches in order to remedy this. Reveiw: Hal Finkel https://reviews.llvm.org/D38886 llvm-svn: 322163
* [MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.Puyan Lotfi2018-01-103-3/+3
| | | | | | | | | | Planning to add support for named vregs. This puts is in a conundrum since physregs are named as well. To rectify this we need to use a sigil other than '%' for physregs in MIR. We've settled on using '$' for physregs but first we must repurpose it from external symbols using it, which is what this commit is all about. We think '&' will have familiar semantics for C/C++ users. llvm-svn: 322146
* Reland "Emit Function IDs table for Control Flow Guard"Adrian McCarthy2018-01-094-0/+110
| | | | | | | | | | | | | | | | | Adds option /guard:cf to clang-cl and -cfguard to cc1 to emit function IDs of functions that have their address taken into a section named .gfids$y for compatibility with Microsoft's Control Flow Guard feature. The original patch didn't have the lit.local.cfg file that restricts the new test to x86, thus the new test was failing on the non-x86 bots. Differential Revision: https://reviews.llvm.org/D40531 The reverts r322008, which was a revert of r322005. This reverts commit a05b89f9aca70597dc79fe97bc49b50b51f525ba. llvm-svn: 322136
* [WebAssembly] Add COMDAT supportSam Clegg2018-01-091-9/+20
| | | | | | | | | | | | | | This adds COMDAT support to the Wasm object-file format. Spec: https://github.com/WebAssembly/tool-conventions/pull/31 Corresponding LLD change: https://bugs.llvm.org/show_bug.cgi?id=35533, and D40845 Patch by Nicholas Wilson Differential Revision: https://reviews.llvm.org/D40844 llvm-svn: 322135
* [DWARFv5] MC support for MD5 file checksumsPaul Robinson2018-01-095-15/+24
| | | | | | | Extend .file directive syntax to allow specifying an MD5 checksum for the source file. Emit the checksums in DWARF v5 line tables. llvm-svn: 322134
* Tidy some grammar in some commentsEric Christopher2018-01-092-4/+4
| | | | llvm-svn: 322133
* [SelectionDAG] Fixed f16-from-vector promotion problemTim Renouf2018-01-091-1/+7
| | | | | | | | | | | | | | | | | | Summary: In the case of an fp_extend of v1f16 to v1f32 where the v1f16 is the result of a bitcast from i16, avoid creating an illegal fp16_to_fp where the input is not a vector and the result is a v1f32. V2: The fix is now to avoid vector scalarization creating a v1->scalar bitcast. Reviewers: srhines, t.p.northover Subscribers: nhaehnle, llvm-commits, dstuttard, t-tye, yaxunl, wdng, kzhuravl, arsenm Differential Revision: https://reviews.llvm.org/D41126 llvm-svn: 322120
* [CodeGen] Don't print "pred:" and "opt:" in -debug outputFrancis Visoiu Mistrih2018-01-093-15/+9
| | | | | | | | | | In -debug output we print "pred:" whenever a MachineOperand is a predicate operand in the instruction descriptor, and "opt:" whenever a MachineOperand is an optional def in the instruction descriptor. Differential Revision: https://reviews.llvm.org/D41870 llvm-svn: 322096
* [CodeGen] Print frame-setup/destroy flags in -debug output like we do in MIRFrancis Visoiu Mistrih2018-01-091-15/+5
| | | | | | | | | | | | | | | Currently the MachineInstr::print function prints the frame-setup/frame-destroy differently than it does in MIR. Instead of: %x21 = LDR %sp, -16; flags: FrameDestroy print: %x21 = frame-destroy LDR %sp, -16 llvm-svn: 322088
* [SelectionDAG] lower math intrinsics to finite version of libcalls when ↵Sanjay Patel2018-01-093-20/+65
| | | | | | | | | | | | | | | | | | | | | | possible (PR35672) Ingredients in this patch: 1. Add HANDLE_LIBCALL defs for finite mathlib functions that correspond to LLVM intrinsics. 2. Plumbing to send TargetLibraryInfo down to SelectionDAGLegalize. 3. Relaxed math and library checking in SelectionDAGLegalize::ConvertNodeToLibcall() to choose finite libcalls. There was a bug about determining the availability of the finite calls that should be fixed with: rL322010 Not in this patch: This doesn't resolve the question/bug of clang creating the intrinsic IR in the first place. There's likely follow-up work needed to support the long double variants better. There's room for improvement to reduce the code duplication. Create finite calls that don't originate from a corresponding intrinsic or DAG node? Differential Revision: https://reviews.llvm.org/D41338 llvm-svn: 322087
* [CodeGen] Don't print register classes in -debug outputFrancis Visoiu Mistrih2018-01-091-37/+0
| | | | | | | | | | Since register classes and banks are already printed with the register definition, don't print it at the end of every instruction anymore. This follows MIR in this regard and is another step to the unification of the two formats. llvm-svn: 322086
* [DAG] Elide overlapping storesNirav Dave2018-01-091-21/+20
| | | | | | | | | | | | | | | | Relanding after fixing handling of pre-indexed memory operations in BaseIndexOffset analysis (r322003). Extend overlapping store elision to handle overwrites of stores by larger stores. Reviewers: craig.topper, rnk, t.p.northover Subscribers: javed.absar, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D40969 llvm-svn: 322085
* [MIR] Add support for the frame-destroy MachineInstr flagFrancis Visoiu Mistrih2018-01-094-0/+8
| | | | | | | | | We are printing / parsing the `frame-setup` MachineInstr flag but not the `frame-destroy` one. Differential Revision: https://reviews.llvm.org/D41509 llvm-svn: 322071
* [CGP] Fix Complex addressing mode for offsetSerguei Katkov2018-01-091-1/+6
| | | | | | | | | | | | | | If the offset is differ in two addressing mode we can continue only if ScaleReg is not set due to we will use it as merge of different offsets. It should fix PR35799 and PR35805. Reviewers: john.brawn, reames Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41227 llvm-svn: 322056
* [MachineOutliner] AArch64: Handle instrs that use SP and will never need fixupsJessica Paquette2018-01-091-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit does two things. Firstly, it adds a collection of flags which can be passed along to the target to encode information about the MBB that an instruction lives in to the outliner. Second, it adds some of those flags to the AArch64 outliner in order to add more stack instructions to the list of legal instructions that are handled by the outliner. The two flags added check if - There are calls in the MachineBasicBlock containing the instruction - The link register is available in the entire block If the link register is available and there are no calls, then a stack instruction can always be outlined without fixups, regardless of what it is, since in this case, the outliner will never modify the stack to create a call or outlined frame. The motivation for doing this was checking which instructions are most often missed by the outliner. Instructions like, say %sp<def> = ADDXri %sp, 32, 0; flags: FrameDestroy are very common, but cannot be outlined in the case that the outliner might modify the stack. This commit allows us to outline instructions like this. llvm-svn: 322048
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