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* Eliminate the use of PriorityQueue and just use a std::vector,Dan Gohman2010-05-262-8/+41
| | | | | | | | implementing pop with a linear search for a "best" element. The priority queue was a neat idea, but in practice the comparison functions depend on dynamic information. llvm-svn: 104718
* Delete an unused function.Dan Gohman2010-05-261-2/+0
| | | | llvm-svn: 104716
* Remove dead code.Devang Patel2010-05-262-11/+1
| | | | llvm-svn: 104706
* Do not construct location list backword!Devang Patel2010-05-261-13/+17
| | | | llvm-svn: 104705
* Temporarily revert r104655 as it's breaking the bots.Eric Christopher2010-05-262-39/+37
| | | | llvm-svn: 104664
* Change push_all to a non-virtual function and implement it in theDan Gohman2010-05-262-6/+1
| | | | | | base class, since all the implementations are the same. llvm-svn: 104659
* Trim #include.Dan Gohman2010-05-261-1/+0
| | | | llvm-svn: 104657
* Dale and Evan suggested putting the "check for setjmp" much earlier in theBill Wendling2010-05-262-37/+39
| | | | | | machine code generation. That's a good idea, so I made it so. llvm-svn: 104655
* First cut at supporting .debug_loc section. Devang Patel2010-05-253-87/+253
| | | | | | This is used to track variable information. llvm-svn: 104649
* Constify function.Bill Wendling2010-05-251-2/+2
| | | | llvm-svn: 104646
* Do one map lookup instead of two.Dan Gohman2010-05-251-2/+3
| | | | llvm-svn: 104645
* Move the verbose asm output up a bit so it can be used in the special casesEric Christopher2010-05-251-5/+6
| | | | | | as well. llvm-svn: 104642
* Okay, bear with me here...Bill Wendling2010-05-251-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If you have a setjmp/longjmp situation, it's possible for stack slot coloring to reuse a stack slot before it's really dead. For instance, if we have something like this: 1: y = g; x = sigsetjmp(env, 0); switch (x) { case 1: /* ... */ goto run; case 0: run: do_run(); /* marked as "no return" */ break; case 3: if (...) { /* ... */ goto run; } /* ... */ break; } 2: g = y; "y" may be put onto the stack, so the expression "g = y" is relying upon the fact that the stack slot containing "y" isn't modified between (1) and (2). But it can be, because of the "no return" calls in there. A longjmp might come back with 3, modify the stack slot, and then go to case 0. And it's perfectly acceptable to reuse the stack slot there because there's no CFG flow from case 3 to (2). The fix is to disable certain optimizations in these situations. Ideally, we'd disable them for all "returns twice" functions. But we don't support that attribute. Check for "setjmp" and "sigsetjmp" instead. llvm-svn: 104640
* Add support for initialized global data for darwin tls. Update commentsEric Christopher2010-05-252-7/+19
| | | | | | and testcases accordingly. llvm-svn: 104635
* Print symbolic SubRegIndex names on machine operands.Jakob Stoklund Olesen2010-05-251-2/+6
| | | | llvm-svn: 104628
* Fix another variant of PR 7191. Also add a testcaseDale Johannesen2010-05-251-1/+5
| | | | | | | | Mon Ping provided; unfortunately bugpoint failed to reduce it, but I think it's important to have a test for this in the suite. 8023512. llvm-svn: 104624
* Fix PR 7191. I have been unable to create a .ll file that fails, sorry.Dale Johannesen2010-05-251-2/+10
| | | | | | | (oye, a word which should be better known to people writing tree traversals, means grandchild.) llvm-svn: 104619
* Disable invalid coalescer assertion.Jakob Stoklund Olesen2010-05-251-1/+4
| | | | llvm-svn: 104574
* Print out the name of the function during SSC.Bill Wendling2010-05-241-1/+5
| | | | llvm-svn: 104572
* Avoid adding duplicate function live-in's.Evan Cheng2010-05-242-2/+17
| | | | llvm-svn: 104560
* Do not emit line number entries for unknown debug values.Devang Patel2010-05-241-0/+3
| | | | | | This fixes recent regression in store.exp from gdb testsuite. llvm-svn: 104524
* Encode the Caml frametable by following what the comment says: the number of ↵Nicolas Geoffray2010-05-241-5/+22
| | | | | | | | descriptors is first emitted, and StackOffsets are emitted in 16 bits. llvm-svn: 104488
* MC: Add an MCLoggingStreamer, for use in debugging integrated-as mismatches.Daniel Dunbar2010-05-231-1/+6
| | | | llvm-svn: 104463
* Implement @llvm.returnaddress. rdar://8015977.Evan Cheng2010-05-221-2/+2
| | | | llvm-svn: 104421
* Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.Jim Grosbach2010-05-221-0/+5
| | | | | | | Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match longjmp. llvm-svn: 104419
* Add full bss data support for darwin tls variables.Eric Christopher2010-05-222-3/+34
| | | | llvm-svn: 104414
* Collect variable information during endFunction() instead of beginFunction().Devang Patel2010-05-221-12/+12
| | | | llvm-svn: 104412
* Clean up extra whitespace.Bob Wilson2010-05-211-1/+0
| | | | llvm-svn: 104410
* Make this LookAheadLimit, not the uninitialized LookAheadLeft.Eric Christopher2010-05-211-1/+1
| | | | | | Evan please verify! llvm-svn: 104408
* Allow machine cse to cse instructions which define physical registers. ↵Evan Cheng2010-05-211-27/+81
| | | | | | Controlled by option -machine-cse-phys-defs. llvm-svn: 104385
* Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elementsBob Wilson2010-05-211-0/+7
| | | | | | | | so that it will continue to test what it was meant to test when I commit a separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon. Fix a DAG combiner crash exposed by this test change. llvm-svn: 104380
* - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defsEvan Cheng2010-05-216-18/+24
| | | | | | | | | | that are aliases of the specified register. - Rename modifiesRegister to definesRegister since it's looking a def of the specific register or one of its super-registers. It's not looking for def of a sub-register or alias that could change the specified register. - Added modifiesRegister to look for defs of aliases. llvm-svn: 104377
* Add MachineInstr::readsWritesVirtualRegister() to determine if an instructionJakob Stoklund Olesen2010-05-211-11/+15
| | | | | | | | | | reads or writes a register. This takes partial redefines and undef uses into account. Don't actually use it yet. That caused miscompiles. llvm-svn: 104372
* SimplifyDevang Patel2010-05-211-44/+23
| | | | llvm-svn: 104338
* constify accessor.Chris Lattner2010-05-211-1/+1
| | | | llvm-svn: 104325
* Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a ↵Jakob Stoklund Olesen2010-05-212-23/+57
| | | | | | | | register is read." This reverts r104322. I think it was causing miscompilations. llvm-svn: 104323
* Use MachineInstr::readsWritesVirtualRegister to determine if a register is read.Jakob Stoklund Olesen2010-05-212-57/+23
| | | | | | This correctly handles partial redefines and undef uses. llvm-svn: 104322
* Teach VirtRegRewriter to handle spilling in instructions that have multipleJakob Stoklund Olesen2010-05-211-1/+7
| | | | | | | | | | | | | definitions of the virtual register. This happens when spilling the registers produced by REG_SEQUENCE: %reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0 The rewriter would spill the register multiple times, dead store elimination tried to keep up, but ended up cutting the branch it was sitting on. llvm-svn: 104321
* If the first definition of a virtual register is a partial redef, add anJakob Stoklund Olesen2010-05-212-6/+23
| | | | | | | <imp-def> operand for the full register. This ensures that the full physical register is marked live after register allocation. llvm-svn: 104320
* Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid.Evan Cheng2010-05-211-1/+1
| | | | llvm-svn: 104306
* Simplify.Devang Patel2010-05-211-16/+8
| | | | llvm-svn: 104302
* Allow targets more controls on what nodes are scheduled by reg pressure, ↵Evan Cheng2010-05-203-14/+25
| | | | | | what for latency in hybrid mode. llvm-svn: 104293
* Refactor.Devang Patel2010-05-202-37/+76
| | | | llvm-svn: 104265
* Remove dbg_value workaround and associated command line optionJim Grosbach2010-05-201-20/+0
| | | | llvm-svn: 104254
* Split DbgVariable. Eventually, variable info will be communicated through ↵Devang Patel2010-05-202-94/+111
| | | | | | frame index, or DBG_VALUE instruction, or collection of DBG_VALUE instructions. Plus each DbgVariable may not need a label. llvm-svn: 104233
* Add a hybrid bottom up scheduler that reduce register usage while avoidingEvan Cheng2010-05-204-28/+141
| | | | | | | | | pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot of long latency instructions so a strict register pressure reduction scheduler does not work well. Early experiments show this speeds up some NEON loops by over 30%. llvm-svn: 104216
* Fix typo in comment.Nick Lewycky2010-05-201-2/+2
| | | | llvm-svn: 104209
* Partial code for emitting thread local bss data.Eric Christopher2010-05-201-0/+7
| | | | llvm-svn: 104197
* Optimize away insertelement of an undef value. This shows up inBob Wilson2010-05-191-0/+4
| | | | | | | test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code because the coalescer cleans it up. Radar 7998853. llvm-svn: 104185
* Enable preserving debug information through post-RA schedulingJim Grosbach2010-05-191-1/+1
| | | | llvm-svn: 104175
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