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* Really really bad local register allocator bug. On X86, it was never using ↵Evan Cheng2008-02-221-1/+1
| | | | | | | | ESI, EDI, and EBP because of a bug in RALocal::isPhysRegAvailable(). For example, when it checks if ESI is available, it then looks at registers aliases to ESI. SIL is marked -2 (not allocatable) but isPhysRegAvailable() incorrectly assumes it is in use and returns false for ESI. llvm-svn: 47499
* Add debugging printfs.Evan Cheng2008-02-221-0/+2
| | | | llvm-svn: 47496
* Make sure reload of implicit uses are issued before remat's.Evan Cheng2008-02-221-3/+15
| | | | llvm-svn: 47492
* Pass alignment on ByVal parameters, from FE, allDale Johannesen2008-02-221-0/+9
| | | | | | the way through. It is now used for codegen. llvm-svn: 47484
* Enable re-materialization of instructions which have virtual register ↵Evan Cheng2008-02-222-39/+187
| | | | | | | | operands if the definition of the operand also reaches its uses. llvm-svn: 47475
* Fix compiler warning.Evan Cheng2008-02-221-1/+1
| | | | llvm-svn: 47468
* Fix a regression in 403.gcc and 186.crafty introduced in 47383. To testDan Gohman2008-02-222-28/+30
| | | | | | | that a value is >= 32, check that all of the high bits are zero, not just one or more. llvm-svn: 47467
* Make the clobber analysis a bit more smart: we only are careful about Chris Lattner2008-02-211-3/+13
| | | | | | | early clobbers if the clobber list contains a *register* not some thing like {memory}, {dirflag} etc. llvm-svn: 47457
* Treat clobber operands like early clobbers: if we haveChris Lattner2008-02-211-0/+16
| | | | | | | | | any, we force sdisel to do all regalloc for an asm. This leads to gross but correct codegen. This fixes the rest of PR2078. llvm-svn: 47454
* Clear PhysRegPartUse for the sub register as well.Bill Wendling2008-02-211-1/+1
| | | | llvm-svn: 47453
* Adjust the MaxAlignment for the special register scavenging spill slot.Bill Wendling2008-02-211-0/+3
| | | | llvm-svn: 47452
* Help testing.Evan Cheng2008-02-211-0/+7
| | | | llvm-svn: 47448
* Better names as per Evan's requestAndrew Lenharth2008-02-211-9/+10
| | | | llvm-svn: 47435
* Atomic op support. If any gcc test uses __sync builtins, it might start ↵Andrew Lenharth2008-02-213-1/+120
| | | | | | failing on archs that haven't implemented them yet llvm-svn: 47430
* Add support for matching mem operands. This fixes PR1133, patch byChris Lattner2008-02-211-1/+7
| | | | | | Eli Friedman. This implements CodeGen/Generic/2008-02-20-MatchingMem.ll. llvm-svn: 47428
* Fix a (harmless) but where vregs were added to the used reg lists for Chris Lattner2008-02-211-9/+26
| | | | | | | | | | inline asms. Fix PR2078 by marking aliases of registers used when a register is marked used. This prevents EAX from being allocated when AX is listed in the clobber set for the asm. llvm-svn: 47426
* Clean up some spilling code using MachineRegisterInfo.Evan Cheng2008-02-211-22/+51
| | | | llvm-svn: 47416
* Remove one of the fixmes that I put in there. From Evan:Bill Wendling2008-02-201-2/+3
| | | | | | | | No need to go up more levels. A def of a register also sets its sub-registers (so if PhysRegInfo[SuperReg] is NULL, it means SuperReg's super registers are not previously defined). llvm-svn: 47399
* Improve some comments explaining the "handle kills" stuff better.Bill Wendling2008-02-201-2/+4
| | | | llvm-svn: 47395
* Fix comment.Bill Wendling2008-02-201-2/+1
| | | | llvm-svn: 47389
* assert is more effective reminder then FIXME tag for unimplemented features.Devang Patel2008-02-201-1/+1
| | | | llvm-svn: 47388
* LegalizeTypes support for scalarizing a vector storeDuncan Sands2008-02-204-8/+46
| | | | | | | | | and splitting extract_subvector. This fixes nine "make check" testcases, for example 2008-02-04-ExtractSubvector.ll and (partially) CodeGen/Generic/vector.ll. llvm-svn: 47384
* Convert Legalize to use the APInt form of ComputeMaskedBits.Dan Gohman2008-02-202-14/+19
| | | | llvm-svn: 47383
* Add explicit keywords.Dan Gohman2008-02-201-1/+1
| | | | llvm-svn: 47382
* Convert DAGCombiner to use the APInt form of ComputeMaskedBits.Dan Gohman2008-02-201-12/+13
| | | | llvm-svn: 47381
* Use APInt::intersects.Dan Gohman2008-02-201-4/+4
| | | | llvm-svn: 47380
* Fix newly-introduced 4.3 warningsAnton Korobeynikov2008-02-202-3/+6
| | | | llvm-svn: 47375
* Update gcc 4.3 warnings fix patch with recent head changesAnton Korobeynikov2008-02-209-26/+44
| | | | llvm-svn: 47368
* Unbreak build with gcc 4.3: provide missed includes and silence most ↵Anton Korobeynikov2008-02-201-0/+1
| | | | | | annoying warnings. llvm-svn: 47367
* Added some comments and reformatted others. No functionality change.Bill Wendling2008-02-201-28/+43
| | | | | | | Added two "FIXMEs" for code that looks dubious to me (but I could be wrong). llvm-svn: 47366
* More constification of things. More comments added. No functionalityBill Wendling2008-02-201-44/+76
| | | | | | changes. (Sorry for any formatting changes that creeped in.) llvm-svn: 47362
* Fix an incredibly subtle bug exposed by Ted's change to APInt profiling.Chris Lattner2008-02-201-1/+1
| | | | | | | | AddNodeIDNode does profiling for a ConstantSDNode, but so does SelectionDAG::getConstant. This profiling should be moved to a common static function in ConstantSDNode. llvm-svn: 47359
* No functionality change:Bill Wendling2008-02-201-31/+42
| | | | | | | - Constified some MachineOperand values. - Added/Modified some comments. llvm-svn: 47358
* Add GetResultInst. First step for multiple return value support.Devang Patel2008-02-191-0/+4
| | | | llvm-svn: 47348
* PR1909: Tail merging pass ran wild. It makes no sense to merge blocks in ↵Evan Cheng2008-02-191-3/+12
| | | | | | order to save a single instruction since a branch will be inserted for each BB. llvm-svn: 47301
* - When DAG combiner is folding a bit convert into a BUILD_VECTOR, it should ↵Evan Cheng2008-02-182-5/+29
| | | | | | | | check if it's essentially a SCALAR_TO_VECTOR. Avoid turning (v8i16) <10, u, u, u> to <10, 0, u, u, u, u, u, u>. Instead, simply convert it to a SCALAR_TO_VECTOR of the proper type. - X86 now normalize SCALAR_TO_VECTOR to (BIT_CONVERT (v4i32 SCALAR_TO_VECTOR)). Get rid of X86ISD::S2VEC. llvm-svn: 47290
* - Remove the previous check which broke coalescer-commute3.llEvan Cheng2008-02-181-5/+5
| | | | | | - For now, conservatively ignore copy MI whose source is a physical register. Commuting its def MI can cause a physical register live interval to be live through a loop (since we know it's live coming into the def MI). llvm-svn: 47281
* New helper function getMBBFromIndex() that given an index in any instruction ↵Roman Levenstein2008-02-181-16/+0
| | | | | | of an MBB returns a pointer the MBB. Reviewed by Evan. llvm-svn: 47267
* For now, avoid commuting def MI for copy MI's whose source is not killed. ↵Evan Cheng2008-02-181-0/+7
| | | | | | That simply trade a live interval for another and because only the non-two-address operands can be folded into loads, may end up pessimising code. llvm-svn: 47262
* I cannot find a libgcc function for this builtin. Therefor expanding it to ↵Andrew Lenharth2008-02-161-5/+15
| | | | | | a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support. llvm-svn: 47213
* Teach LegalizeTypes how to expand the operands ofDuncan Sands2008-02-162-4/+25
| | | | | | br_cc. This fixes 5 "make check" failures. llvm-svn: 47212
* Refactor some code; check if commuteInstruction is able to commute the ↵Evan Cheng2008-02-162-17/+34
| | | | | | instruction. llvm-svn: 47208
* llvm.memory.barrier, and impl for x86 and alphaAndrew Lenharth2008-02-163-0/+20
| | | | llvm-svn: 47204
* Fix typos.Bill Wendling2008-02-161-2/+2
| | | | llvm-svn: 47200
* Rename CountMemOperands to ComputeMemOperandsEnd to reflect whatDan Gohman2008-02-161-12/+9
| | | | | | | it actually does. Simplify CountOperands a little by reusing ComputeMemOperandsEnd. And reword some comments for both. llvm-svn: 47198
* Revert 47177, which was incorrect.Dan Gohman2008-02-161-1/+1
| | | | llvm-svn: 47196
* Make tblgen a little smarter about constants smaller than i32. Currently,Scott Michel2008-02-151-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | tblgen will complain if a sign-extended constant does not fit into a data type smaller than i32, e.g., i16. This causes a problem when certain hex constants are used, such as 0xff for byte masks or immediate xor values. tblgen will try the sign-extended value first and, if the sign extended value would overflow, it tries to see if the unsigned value will fit. Consequently, a software developer can now safely incant: (XORHIr16 R16C:$rA, 0xffff) which is somewhat clearer and more informative than incanting: (XORHIr16 R16C:$rA, (i16 -1)) even if the two are bitwise equivalent. Tblgen also outputs the 64-bit unsigned constant in the generated ISel code when getTargetConstant() is invoked. llvm-svn: 47188
* The copy instruction being coalesced will be removed, it is not a kill.Evan Cheng2008-02-151-2/+2
| | | | llvm-svn: 47179
* Skip over the defs and start at the uses when looking for operandsDan Gohman2008-02-151-1/+1
| | | | | | with the TIED_TO attribute. llvm-svn: 47177
* Use the TargetInstrDescr to determine the number of operandsDan Gohman2008-02-151-3/+3
| | | | | | | that should be checked for the TIED_TO attribute instead of using CountOperands. llvm-svn: 47176
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