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* Make insert_subreg a two-address instruction, vastly simplifying ↵Christopher Lamb2008-03-162-141/+89
| | | | | | LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register. llvm-svn: 48412
* Remove isImplicitDef TargetInstrDesc flag.Evan Cheng2008-03-151-4/+3
| | | | llvm-svn: 48381
* Replace all target specific implicit def instructions with a target ↵Evan Cheng2008-03-152-4/+18
| | | | | | independent one: TargetInstrInfo::IMPLICIT_DEF. llvm-svn: 48380
* Do not generate special entries in the dwarf ehDuncan Sands2008-03-141-6/+2
| | | | | | table for nounwind calls. llvm-svn: 48373
* Fix PR2138. Apparently any modification to a std::multimap (including remove ↵Evan Cheng2008-03-141-2/+8
| | | | | | entries for a different key) can invalidate multimap iterators. llvm-svn: 48371
* Simplify using getIntPtrConstant.Duncan Sands2008-03-141-5/+3
| | | | llvm-svn: 48355
* Tabs -> spacesNate Begeman2008-03-141-14/+23
| | | | | | | Use getIntPtrConstant in a couple places to shorten stuff up Handle splitting vector shuffles with undefs in the mask llvm-svn: 48351
* Livein copy scheduling fixes: do not coalesce physical register copies, ↵Evan Cheng2008-03-141-112/+42
| | | | | | correctly determine the safe location to insert the copies. llvm-svn: 48348
* More APInt-ification.Dan Gohman2008-03-135-67/+77
| | | | llvm-svn: 48344
* Undo tweak. It had no obvious benefit.Evan Cheng2008-03-131-19/+4
| | | | llvm-svn: 48341
* Typo.Evan Cheng2008-03-131-1/+1
| | | | llvm-svn: 48337
* Don't try to sink 3-address instruction if convertToThreeAddress created ↵Evan Cheng2008-03-131-1/+6
| | | | | | more than one instructions. llvm-svn: 48336
* Remove an unused command line option.Evan Cheng2008-03-131-9/+0
| | | | llvm-svn: 48334
* TwoAddressInstructionPass enhancement. After it converts a two address ↵Evan Cheng2008-03-131-13/+131
| | | | | | instruction into a 3-address one, sink it past the instruction that kills the read-mod-write register if its definition is used past the kill. This reduces the number of live register by one. llvm-svn: 48333
* Get rid of a pseudo instruction and replace it with subreg based operation ↵Christopher Lamb2008-03-131-10/+14
| | | | | | | on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes. llvm-svn: 48329
* Remove unused options.Evan Cheng2008-03-131-13/+0
| | | | llvm-svn: 48319
* Refactor some code out of MachineSink into a MachineInstr query.Evan Cheng2008-03-132-29/+38
| | | | llvm-svn: 48311
* Experimental scheduler change to schedule / coalesce the copies added for ↵Evan Cheng2008-03-121-23/+181
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | function livein's. Take 2008-03-10-RegAllocInfLoop.ll, the schedule looks like this after these copies are inserted: entry: 0x12049d0, LLVM BB @0x1201fd0, ID#0: Live Ins: %EAX %EDX %ECX %reg1031<def> = MOVPC32r 0 %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def> %reg1028<def> = MOV32rr %EAX %reg1029<def> = MOV32rr %EDX %reg1030<def> = MOV32rr %ECX %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x1201910 + 0] %reg1025<def> = MOV32rr %reg1029 %reg1026<def> = MOV32rr %reg1030 %reg1024<def> = MOV32rr %reg1028 The copies unnecessarily increase register pressure and it will end up requiring a physical register to be spilled. With -schedule-livein-copies: entry: 0x12049d0, LLVM BB @0x1201fa0, ID#0: Live Ins: %EAX %EDX %ECX %reg1031<def> = MOVPC32r 0 %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def> %reg1024<def> = MOV32rr %EAX %reg1025<def> = MOV32rr %EDX %reg1026<def> = MOV32rr %ECX %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x12018e0 + 0] Much better! llvm-svn: 48307
* Initial soft-float support for LegalizeTypes. I rewroteDuncan Sands2008-03-126-34/+248
| | | | | | | | | | | | | | | | | | | | | the fcopysign expansion from LegalizeDAG to get rid of what seems to be a bug: the use of sign extension means that when copying the sign bit from an f32 to an f64, the upper 32 bits of the f64 (now an i64) are set, not just the top bit... I also generalized it to work for any sized floating point types, and removed the bogosity: SDOperand Mask1 = (SrcVT == MVT::f64) ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); (here SrcNVT is an integer with the same size as SrcVT). As far as I can see this takes a 1 << 63, converts to a double, converts that to a floating point constant then converts that to an integer constant, ending up with... 1 << 63 as an integer constant! So I just generate this integer constant directly. llvm-svn: 48305
* Change VirtRegMap's dump to dump to cerr, not DOUT, so that itDan Gohman2008-03-121-1/+1
| | | | | | | can be called from within a debuger without having -debug specified on the command-line. llvm-svn: 48298
* Fix typos in comments.Dan Gohman2008-03-121-2/+2
| | | | llvm-svn: 48297
* Fix typo.Duncan Sands2008-03-121-1/+1
| | | | llvm-svn: 48295
* Don't try to extract an i32 from an f64. ThisDuncan Sands2008-03-122-12/+22
| | | | | | | | | | | | getCopyToParts problem was noticed by the new LegalizeTypes infrastructure. In order to avoid this kind of thing in the future I've added a check that EXTRACT_ELEMENT is only used with integers. Once LegalizeTypes is up and running most likely BUILD_PAIR and EXTRACT_ELEMENT can be removed, in favour of using apints instead. llvm-svn: 48294
* Clean up my own mess.Evan Cheng2008-03-121-7/+1
| | | | | | X86 lowering normalize vector 0 to v4i32. However DAGCombine can fold (sub x, x) -> 0 after legalization. It can create a zero vector of a type that's not expected (e.g. v8i16). We don't want to disable the optimization since leaving a (sub x, x) is really bad. Add isel patterns for other types of vector 0 to ensure correctness. It's highly unlikely to happen other than in bugpoint reduced test cases. llvm-svn: 48279
* We also need to collect the VN IDs for the PHI instructions for later updating.Owen Anderson2008-03-121-1/+10
| | | | llvm-svn: 48278
* When we're determining what registers to coallesce, track the VNInfo IDs for ↵Owen Anderson2008-03-121-16/+32
| | | | | | | | the definitions that feed the PHI instructions. We'll need these IDs in order to update LiveIntervals properly. llvm-svn: 48277
* Total brain cramp.Evan Cheng2008-03-121-1/+1
| | | | llvm-svn: 48274
* Set NextMII after issuing a physical register spill.Evan Cheng2008-03-121-0/+1
| | | | llvm-svn: 48263
* Minor debug output bug.Evan Cheng2008-03-121-1/+1
| | | | llvm-svn: 48261
* Correctly propagate thread-local flag from aliasee to alias. This fixes PR2137Anton Korobeynikov2008-03-111-1/+10
| | | | llvm-svn: 48257
* Use PassManagerBase instead of FunctionPassManager for functionsDan Gohman2008-03-113-7/+7
| | | | | | | | that merely add passes. This allows them to be used with either FunctionPassManager or PassManager, or even with a custom new kind of pass manager. llvm-svn: 48256
* Honour aliases visibility during asm emissionAnton Korobeynikov2008-03-111-1/+9
| | | | llvm-svn: 48249
* Transfer physical register spill info when load / store folding happens.Evan Cheng2008-03-113-1/+20
| | | | llvm-svn: 48246
* Use the correct value for InSignBit.Dan Gohman2008-03-111-1/+1
| | | | llvm-svn: 48245
* Initial codegen support for functions and calls with multiple return values.Dan Gohman2008-03-111-18/+51
| | | | llvm-svn: 48244
* Recommitting parts of r48130. These do not appear to cause the observed ↵Christopher Lamb2008-03-112-39/+26
| | | | | | failures. llvm-svn: 48223
* Use TargetRegisterInfo::getPhysicalRegisterRegClass. Remove duplicated code.Evan Cheng2008-03-111-21/+6
| | | | llvm-svn: 48221
* When the register allocator runs out of registers, spill a physical register ↵Evan Cheng2008-03-116-9/+186
| | | | | | around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting. llvm-svn: 48218
* Some LegalizeTypes code factorization and minorDuncan Sands2008-03-115-56/+113
| | | | | | enhancements. llvm-svn: 48215
* compile: double test() {}Chris Lattner2008-03-111-1/+3
| | | | | | | | | | | | | | | | | | | | into: _test: fldz ret instead of: _test: subl $12, %esp #IMPLICIT_DEF %xmm0 movsd %xmm0, (%esp) fldl (%esp) addl $12, %esp ret llvm-svn: 48213
* variadic instructions don't have operand info for variadic arguments.Chris Lattner2008-03-111-1/+2
| | | | llvm-svn: 48208
* Generalize ExpandIntToFP to handle the case where the operand is legalDan Gohman2008-03-111-11/+22
| | | | | | | | and it's the result that requires expansion. This code is a little confusing because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type (the integer type) rather than the result type. llvm-svn: 48206
* If a register operand comes from the variadic part of a node, don'tChris Lattner2008-03-111-4/+6
| | | | | | verify the register constraint matches what the instruction expects. llvm-svn: 48205
* Temporarily revert 48175.Evan Cheng2008-03-111-7/+1
| | | | llvm-svn: 48204
* More APInt-ification.Dan Gohman2008-03-111-7/+7
| | | | llvm-svn: 48201
* Correctly clone FlaggedNodes.Dan Gohman2008-03-101-2/+1
| | | | llvm-svn: 48196
* APInt-ify this.Dan Gohman2008-03-101-3/+4
| | | | llvm-svn: 48194
* Implement more support for fp-to-i128 and i128-to-fp conversions. Dan Gohman2008-03-102-80/+133
| | | | llvm-svn: 48189
* If the register allocator ran out of registers, just abort for now.Evan Cheng2008-03-101-1/+7
| | | | llvm-svn: 48175
* Fix mul expansion to check the correct number of bits forDan Gohman2008-03-101-4/+3
| | | | | | | zero extension when checking if an unsigned multiply is safe. llvm-svn: 48171
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