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* Somewhat better solution.Evan Cheng2008-03-101-3/+4
| | | | llvm-svn: 48170
* Default ISD::PREFETCH to expand.Evan Cheng2008-03-101-0/+3
| | | | llvm-svn: 48169
* Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.Evan Cheng2008-03-102-27/+38
| | | | llvm-svn: 48167
* Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC'sScott Michel2008-03-106-50/+66
| | | | | | | | return ValueType can depend its operands' ValueType. This is a cosmetic change, no functionality impacted. llvm-svn: 48145
* Minor cleanup. No functionality change.Bill Wendling2008-03-101-6/+8
| | | | llvm-svn: 48142
* - Fix a subtle bug in RemoveCopyByCommutingDef. ALR is the live range where ↵Evan Cheng2008-03-102-7/+56
| | | | | | | | | | | | | | | | | | the source is defined; BLR is the live range which is defined by the copy. If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g. A = or A, B ... B = A ... C = A<kill> ... = B then do not add kills of A to the newly created B interval. - Also fix some kill info update bug. llvm-svn: 48141
* DohEvan Cheng2008-03-101-1/+2
| | | | llvm-svn: 48140
* Move StrongPHIElimination after live interval analysis. This will make ↵Owen Anderson2008-03-101-36/+27
| | | | | | things happier down the road. llvm-svn: 48138
* Avoid creating BUILD_VECTOR of all zero elements of "non-normalized" type ↵Evan Cheng2008-03-101-0/+4
| | | | | | (e.g. v8i16 on x86) after legalizer. Instruction selection does not expect to see them. In all likelihood this can only be an issue in a bugpoint reduced test case. llvm-svn: 48136
* Allow insert_subreg into implicit, target-specific values. Christopher Lamb2008-03-102-38/+27
| | | | | | | Change insert/extract subreg instructions to be able to be used in TableGen patterns. Use the above features to reimplement an x86-64 pseudo instruction as a pattern. llvm-svn: 48130
* Increase ISD::ParamFlags to 64 bits. Increase the ByValSizeDale Johannesen2008-03-102-16/+24
| | | | | | | | | | field to 32 bits, thus enabling correct handling of ByVal structs bigger than 0x1ffff. Abstract interface a bit. Fixes gcc.c-torture/execute/pr23135.c and gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing on ppc32, quietly producing wrong code on x86-32.) llvm-svn: 48122
* remove an extraneous (and ugly) default argument, thanks Duncan.Chris Lattner2008-03-091-2/+1
| | | | llvm-svn: 48117
* fp_round's produced by getCopyFromParts should always be exact, becauseChris Lattner2008-03-091-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | they are produced by calls (which are known exact) and by cross block copies which are known to be produced by extends. This improves: define double @test2() { %tmp85 = call double asm sideeffect "fld0", "={st(0)}"() ret double %tmp85 } from: _test2: subl $20, %esp # InlineAsm Start fld0 # InlineAsm End fstpl 8(%esp) movsd 8(%esp), %xmm0 movsd %xmm0, (%esp) fldl (%esp) addl $20, %esp #FP_REG_KILL ret to: _test2: # InlineAsm Start fld0 # InlineAsm End #FP_REG_KILL ret by avoiding a f64 <-> f80 trip llvm-svn: 48108
* teach X86InstrInfo::copyRegToReg how to copy into ST(0) from Chris Lattner2008-03-091-15/+23
| | | | | | | | | | | | an RFP register class. Teach ScheduleDAG how to handle CopyToReg with different src/dst reg classes. This allows us to compile trivial inline asms that expect stuff on the top of x87-fp stack. llvm-svn: 48107
* Add ScheduleDAG support for copytoreg where the src/dst register areChris Lattner2008-03-091-16/+19
| | | | | | | | in different register classes, e.g. copy of ST(0) to RFP*. This gets some really trivial inline asm working that plops things on the top of stack (PR879) llvm-svn: 48105
* fix 80 col violationChris Lattner2008-03-091-1/+2
| | | | llvm-svn: 48100
* extend fp values with FP_EXTEND not FP_ROUND.Chris Lattner2008-03-091-3/+6
| | | | llvm-svn: 48097
* Fix two problems in SelectionDAGLegalize::ExpandBUILD_VECTOR's handlingChris Lattner2008-03-091-21/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | of BUILD_VECTORS that only have two unique elements: 1. The previous code was nondeterminstic, because it walked a map in SDOperand order, which isn't determinstic. 2. The previous code didn't handle the case when one element was undef very well. Now we ensure that the generated shuffle mask has the undef vector on the RHS (instead of potentially being on the LHS) and that any elements that refer to it are themselves undef. This allows us to compile CodeGen/X86/vec_set-9.ll into: _test3: movd %rdi, %xmm0 punpcklqdq %xmm0, %xmm0 ret instead of: _test3: movd %rdi, %xmm1 #IMPLICIT_DEF %xmm0 punpcklqdq %xmm1, %xmm0 ret ... saving a register. llvm-svn: 48060
* Teach SD some vector identities, allowing us to compile vec_set-9 into:Chris Lattner2008-03-081-1/+13
| | | | | | | | | | | | | | | | | | | | | _test3: movd %rdi, %xmm1 #IMPLICIT_DEF %xmm0 punpcklqdq %xmm1, %xmm0 ret instead of: _test3: #IMPLICIT_DEF %rax movd %rax, %xmm0 movd %rdi, %xmm1 punpcklqdq %xmm1, %xmm0 ret This is still not ideal. There is no reason to two xmm regs. llvm-svn: 48058
* Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} ↵Evan Cheng2008-03-083-4/+29
| | | | | | and prefetchnta instructions. llvm-svn: 48042
* Something that kills a super-register alsoBill Wendling2008-03-071-2/+1
| | | | | | kills the sub-register. llvm-svn: 48038
* Fixed a register scavenger bug. If a def is re-defining part of a super ↵Evan Cheng2008-03-071-3/+8
| | | | | | register, there must be an implicit def of the super-register on the MI. llvm-svn: 48024
* When setting the "unused" info, take into account something like this:Bill Wendling2008-03-061-8/+38
| | | | | | | | %r3<def> = OR %x3<kill>, %x3 We don't want to mark the %r3 as unused even though it's a sub-register of %x3. llvm-svn: 48003
* 80 col violation.Evan Cheng2008-03-061-2/+4
| | | | llvm-svn: 47998
* some more spelling changesGabor Greif2008-03-061-1/+1
| | | | llvm-svn: 47996
* Constant fold SIGN_EXTEND_INREG with ashr not lshr.Evan Cheng2008-03-061-1/+1
| | | | llvm-svn: 47992
* Fix a coalescer bug wrt how dead copy interval is shortened.Evan Cheng2008-03-052-13/+36
| | | | llvm-svn: 47966
* Clarify that CALLSEQ_START..END may not be nested,Dale Johannesen2008-03-051-0/+7
| | | | | | and add some protection against creating such. llvm-svn: 47957
* Generalize FP constant shrinking optimization to apply to any vtChris Lattner2008-03-051-26/+25
| | | | | | | | except ppc long double. This allows us to shrink constant pool entries for x86 long double constants, which in turn allows us to use flds/fldl instead of fldt. llvm-svn: 47938
* Improve comment, pass in the original VT so that we can shrink a long double ↵Chris Lattner2008-03-051-2/+4
| | | | | | | | constant all the way to float, not stopping at double. llvm-svn: 47937
* Codegen support for i128 UINT_TO_FP. This just fixes aDan Gohman2008-03-052-6/+2
| | | | | | | | bug in r47928 (Int64Ty is the correct type for the constant pool entry here) and removes the asserts, now that the code is capable of handling i128. llvm-svn: 47932
* Add a target lowering hook to control whether it's worthwhile to compress fp ↵Evan Cheng2008-03-051-1/+2
| | | | | | | | constant. For x86, if sse2 is available, it's not a good idea since cvtss2sd is slower than a movsd load and it prevents load folding. On x87, it's important to shrink fp constant since fldt is very expensive. llvm-svn: 47931
* 64bit CAS on 32bit x86.Andrew Lenharth2008-03-051-0/+11
| | | | llvm-svn: 47929
* Codegen support for i128 SINT_TO_FP.Dan Gohman2008-03-053-21/+56
| | | | llvm-svn: 47928
* Refactor code. Remove duplicated functions that basically do the same thing asEvan Cheng2008-03-0511-149/+102
| | | | | | findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies. llvm-svn: 47927
* Some improvements related to the computation of heights, depths of SUnits.Roman Levenstein2008-03-041-21/+93
| | | | | | | The basic idea is that all these algorithms are computing the longest paths from the root node or to the exit node. Therefore the existing implementation that uses and iterative and potentially exponential algorithm was changed to a well-known graph algorithm based on dynamic programming. It has a linear run-time. llvm-svn: 47884
* Refactor ExpandConstantFP so it can optimize load from constpool of types ↵Evan Cheng2008-03-041-16/+19
| | | | | | larger than f64 into extload from smaller types. llvm-svn: 47883
* Did I say 'e = getNumOperands()'? I meant --e, of course.Bill Wendling2008-03-041-1/+1
| | | | llvm-svn: 47875
* Rename isOperand() to isOperandOf() (and other similar methods). It always ↵Evan Cheng2008-03-044-17/+17
| | | | | | confuses me. llvm-svn: 47872
* Miscellaneous clean-ups based on Evan's feedback:Bill Wendling2008-03-032-65/+79
| | | | | | | | | - Cleaned up how the prologue-epilogue inserter loops over the instructions. - Instead of restarting the processing of an instruction if we remove an implicit kill, just update the end iterator and make sure that the iterator isn't incremented. llvm-svn: 47870
* Misc. APInt-ification in the DAGCombiner.Dan Gohman2008-03-031-17/+20
| | | | llvm-svn: 47869
* More APInt-ification.Dan Gohman2008-03-031-10/+6
| | | | llvm-svn: 47868
* Yet more APInt-ification.Dan Gohman2008-03-031-9/+6
| | | | llvm-svn: 47867
* More APInt-ification.Dan Gohman2008-03-031-16/+19
| | | | llvm-svn: 47866
* More APInt-ification.Dan Gohman2008-03-031-3/+4
| | | | llvm-svn: 47864
* Go through the machine instruction's operands to make sure that we're notBill Wendling2008-03-031-12/+52
| | | | | | | marking both a super- and sub-register as "killed". This removes implicit uses that are marked as "killed". llvm-svn: 47862
* Make the register scavenger update the bookkeeping values for sub/superBill Wendling2008-03-031-3/+39
| | | | | | registers. llvm-svn: 47861
* Multiple instructions can be inserted when eliminating frame indexes. We needBill Wendling2008-03-031-7/+24
| | | | | | | the register scavenger to process all of those new instructions instead of just the last one inserted. llvm-svn: 47860
* all but CAS working on x86Andrew Lenharth2008-03-011-13/+14
| | | | llvm-svn: 47798
* Add MVT::is128BitVector and is64BitVector. ShrinkDale Johannesen2008-03-011-16/+5
| | | | | | | unaligned load/store code using them. Per review of unaligned load/store vector patch. llvm-svn: 47782
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