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* Renamed Spiller classes (plus uses and related files) to VirtRegRewriter.Lang Hames2009-05-066-2244/+2206
| | | | llvm-svn: 71057
* If a MachineBasicBlock has multiple ways of reaching another block,Dan Gohman2009-05-052-9/+5
| | | | | | | | allow it to have multiple CFG edges to that block. This is needed to allow MachineBasicBlock::isOnlyReachableByFallthrough to work correctly. This fixes PR4126. llvm-svn: 71018
* Enable stack coloring with regs at -O3.Evan Cheng2009-05-052-10/+22
| | | | llvm-svn: 71010
* Do not require variable debug info nodes to have a compile unit.Chris Lattner2009-05-051-20/+24
| | | | | | | For implicit decls like "self" and "_cmd" in ObjC, these decls should not have a location. llvm-svn: 70964
* Do not substitute if the new register isn't in the register class of the ↵Evan Cheng2009-05-051-0/+14
| | | | | | operand being updated. llvm-svn: 70953
* Move getInstrOperandRegClass from the scheduler to TargetInstrInfo.Evan Cheng2009-05-052-26/+0
| | | | llvm-svn: 70950
* Do forward and backward substitution to eliminate loads and stores when ↵Evan Cheng2009-05-041-13/+127
| | | | | | possible. llvm-svn: 70937
* Make DBG_STOPPOINT nodes, and therefore DBG_LABEL labels, get a DebugLoc, so ↵Chris Lattner2009-05-042-6/+8
| | | | | | | | | that it shows up in -print-machineinstrs. This doesn't appear to affect anything, but it was weird for some DBG_LABELs to have DebugLocs but not all of them. llvm-svn: 70921
* Restore a comment.Argyrios Kyrtzidis2009-05-041-0/+2
| | | | llvm-svn: 70900
* -Remove the DwarfWriter::RecordSourceLine calls from the instruction selectors.Argyrios Kyrtzidis2009-05-043-16/+10
| | | | | | | | -Depend on DebugLocs for source line info. (Comes with Regression-Be-Gone(tm)) llvm-svn: 70871
* Make sure to color with only allocatable registers for the specific register ↵Evan Cheng2009-05-042-2/+15
| | | | | | class. llvm-svn: 70821
* The stack slots which share the same stack slot after coloring can, but do ↵Evan Cheng2009-05-041-44/+37
| | | | | | not have to, use the same register. In fact, they each may have different register class requirements. llvm-svn: 70815
* Revert r70803 for now, it causes a regression.Argyrios Kyrtzidis2009-05-033-2/+16
| | | | llvm-svn: 70811
* -Remove the DwarfWriter::RecordSourceLine calls from the instruction selectors.Argyrios Kyrtzidis2009-05-033-16/+2
| | | | | | -Depend on DebugLocs for source line info. llvm-svn: 70803
* Typo.Evan Cheng2009-05-031-1/+1
| | | | llvm-svn: 70792
* In some rare cases, the register allocator can spill registers but end up ↵Evan Cheng2009-05-038-144/+427
| | | | | | | | | | not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all. VirtRegMap keeps track of allocations so it knows what's not used. As a horrible hack, the stack coloring can color spill slots with *free* registers. That is, it replace reload and spills with copies from and to the free register. It unfold instructions that load and store the spill slot and replace them with register using variants. Not yet enabled. This is part 1. More coming. llvm-svn: 70787
* Fix typoAnton Korobeynikov2009-05-031-1/+1
| | | | llvm-svn: 70770
* Properly handle sdiv / udiv / srem / urem libcallsAnton Korobeynikov2009-05-032-7/+15
| | | | llvm-svn: 70764
* Proper name 16 bit libcallsAnton Korobeynikov2009-05-031-4/+4
| | | | llvm-svn: 70750
* Add libcall expansion for 16 and 128 bit mulsAnton Korobeynikov2009-05-031-0/+4
| | | | llvm-svn: 70749
* -Move the DwarfWriter::ValidDebugInfo check to a static ↵Argyrios Kyrtzidis2009-05-033-191/+117
| | | | | | | | DIDescriptor::ValidDebugInfo -Create DebugLocs without the need to have a DwarfWriter around llvm-svn: 70682
* Allow CONCAT_VECTORS nodes to be legal or have custom lowering for some targets.Bob Wilson2009-05-012-14/+38
| | | | | | Changes to take advantage of this will come later. llvm-svn: 70560
* Simplify more code and add timer stuff.Bill Wendling2009-05-011-7/+32
| | | | llvm-svn: 70539
* Simplify more code.Bill Wendling2009-05-011-9/+4
| | | | llvm-svn: 70537
* Simplify some code.Bill Wendling2009-05-011-8/+5
| | | | llvm-svn: 70534
* Fix whitespace. It was confusing me.Bill Wendling2009-05-011-21/+20
| | | | llvm-svn: 70533
* Code clean up. Bye bye PhysRegTracker.Evan Cheng2009-05-012-99/+83
| | | | llvm-svn: 70524
* Make DebugLoc independent of DwarfWriter.Argyrios Kyrtzidis2009-04-306-62/+44
| | | | | | | | -Replace DebugLocTuple's Source ID with CompileUnit's GlobalVariable* -Remove DwarfWriter::getOrCreateSourceID -Make necessary changes for the above (fix callsites, etc.) llvm-svn: 70520
* Join cross class copies using getCommonSubClass()Jakob Stoklund Olesen2009-04-301-20/+8
| | | | llvm-svn: 70513
* Add a smarter heuristic to determine when to coalesce a virtual register ↵Evan Cheng2009-04-302-20/+173
| | | | | | | | with a physical one. More specifically, it avoid tying a virtual register in the loop with a physical register defined / used outside the loop. When it determines it's not profitable, it will use the physical register as the allocation preference instead. This is *not* turned on by default. Testing indicates this is just as likely to pessimize code. The main issue seems to be allocation preference doesn't work effectively. That will change once I've taught register allocator "swapping". llvm-svn: 70503
* Move helper functions for optimizing division by constant into the APIntJay Foad2009-04-301-101/+2
| | | | | | class. llvm-svn: 70488
* fix a regression handling indirect results: these need to be consideredChris Lattner2009-04-301-8/+13
| | | | | | | | memory operands otherwise the writebacks get lost when the inline asm doesn't otherwise have side effects. This fixes rdar://6839427, though clang really shouldn't generate these anymore. llvm-svn: 70455
* Instead of passing in an unsigned value for the optimization level, use an enum,Bill Wendling2009-04-2912-51/+53
| | | | | | | which better identifies what the optimization is doing. And is more flexible for future uses. llvm-svn: 70440
* Fix infinite recursion in the C++ code which handles movddup by making it ↵Nate Begeman2009-04-291-2/+2
| | | | | | unnecessary. llvm-svn: 70425
* MachineInstr::isRegTiedTo{Use,Def}Operand can safely be made const.Jakob Stoklund Olesen2009-04-291-2/+4
| | | | llvm-svn: 70408
* Update comment, replace theoretically impossible check with an assert.Nate Begeman2009-04-291-3/+1
| | | | llvm-svn: 70391
* spillPhysRegAroundRegDefsUses() may have invalidated iterators stored in ↵Evan Cheng2009-04-291-0/+9
| | | | | | fixed_ IntervalPtrs. Reset them. llvm-svn: 70378
* Implement review feedback for vector shuffle work.Nate Begeman2009-04-296-96/+105
| | | | llvm-svn: 70372
* Add a public method called getAddressSpace() to the GlobalAddressSDNode.Sanjiv Gupta2009-04-291-0/+7
| | | | llvm-svn: 70366
* Disable the load-shrinking optimization from looking atChris Lattner2009-04-291-3/+6
| | | | | | | | | | | anything larger than 64-bits, avoiding a crash. This should really be fixed to use APInts, though type legalization happens to help us out and we get good code on the attached testcase at least. This fixes rdar://6836460 llvm-svn: 70360
* Determine allocation 'preference' with right register class. I haven't seen ↵Evan Cheng2009-04-291-8/+10
| | | | | | this changing codegen so no test case. llvm-svn: 70351
* Second attempt:Bill Wendling2009-04-2912-85/+88
| | | | | | | | | | | | Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to use the old behavior, the flag is -O0. This change allows for finer-grained control over which optimizations are run at different -O levels. Most of this work was pretty mechanical. The majority of the fixes came from verifying that a "fast" variable wasn't used anymore. The JIT still uses a "Fast" flag. I'll change the JIT with a follow-up patch. llvm-svn: 70343
* Move getMatchingSuperReg() out of coalescer and into TargetRegisterInfo.Evan Cheng2009-04-281-16/+4
| | | | llvm-svn: 70309
* Don't coalesce a physical register with an incompatible virtual register.Jakob Stoklund Olesen2009-04-281-5/+42
| | | | | | | | | | If the physical register does not belong to the virtual register's regclass, don't coalesce. The physical register could be an invalid operand for an instruction using the vreg. The regclass matching is done after determining the actual subregisters being copied. llvm-svn: 70298
* Initialized arrays can be in any address space.Sanjiv Gupta2009-04-281-3/+4
| | | | llvm-svn: 70297
* Move getSubRegisterRegClass from ScheduleDagSDNodesEmit.cpp to a ↵Jakob Stoklund Olesen2009-04-281-14/+3
| | | | | | | | | | TargetRegisterClass method. Also make the method non-asserting. It will return NULL when given an invalid subreg index. The method is needed by an upcoming patch. llvm-svn: 70296
* Fix PR4034. Bug in LiveInterval::join when it's compacting new valno's.Evan Cheng2009-04-281-1/+1
| | | | llvm-svn: 70291
* Fix for PR4051. When 2address pass delete an instruction, update kill info ↵Evan Cheng2009-04-281-8/+79
| | | | | | when necessary. llvm-svn: 70279
* r70270 isn't ready yet. Back this out. Sorry for the noise.Bill Wendling2009-04-2812-87/+85
| | | | llvm-svn: 70275
* Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want toBill Wendling2009-04-2812-84/+87
| | | | | | | | | | | use the old behavior, the flag is -O0. This change allows for finer-grained control over which optimizations are run at different -O levels. Most of this work was pretty mechanical. The majority of the fixes came from verifying that a "fast" variable wasn't used anymore. The JIT still uses a "Fast" flag. I'm not 100% sure if it's necessary to change it there... llvm-svn: 70270
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