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* It turns out that putting an 8-byte symbol in a 4-byte section makes Solaris ↵David Chisnall2012-02-171-3/+3
| | | | | | | | | ld sulk. GNU ld is perfectly happy with it, which is worrying for a whole other set of reasons... Thanks to Anton, Duncan and Rafael for helping me track this down. Pointy hat to Rafael for introducing the bug in the first place. llvm-svn: 150811
* Reverse iterator - should be incrementing rather than decrementing.Lang Hames2012-02-171-2/+2
| | | | llvm-svn: 150778
* MachineScheduler shouldn't use/preserve LiveDebugVariables.Lang Hames2012-02-171-4/+0
| | | | llvm-svn: 150773
* Oops - isRegLiveIntoSuccessor is used in non-assert builds now. Remove ↵Lang Hames2012-02-171-2/+0
| | | | | | NDEBUG guards. llvm-svn: 150771
* Re-enable 150652 and 150654 - Make FPSCR non-reserved, and make MachineCSE ↵Lang Hames2012-02-171-3/+9
| | | | | | bail on reserved registers. This *should* be safe as of r150786. llvm-svn: 150769
* Turn off assertion, conservatively compute liveness for live-in ↵Lang Hames2012-02-171-8/+10
| | | | | | un-allocatable registers. llvm-svn: 150768
* Disable machine copy propagation for now. It's known to be buggy (PR11940) ↵Benjamin Kramer2012-02-161-1/+1
| | | | | | and introduces subtle miscompiles in many places. llvm-svn: 150703
* Remove extraneous #include and spelling mistake introduced in r150669.James Molloy2012-02-161-2/+1
| | | | llvm-svn: 150670
* Modify the algorithm when traversing the DAGCombiner's worklist to be O(log ↵James Molloy2012-02-161-13/+36
| | | | | | N) for all operations. This fixes a horrible worst case with lots of nodes where 99% of the time was being spent in std::remove. llvm-svn: 150669
* Oop - r150653 + r150654 broke one of my test cases. Backing out for now...Lang Hames2012-02-161-9/+3
| | | | llvm-svn: 150655
* MachineCSE shouldn't extend the live ranges of reserved or allocatable ↵Lang Hames2012-02-161-3/+9
| | | | | | registers. llvm-svn: 150653
* Handle register masks in branch folding.Jakob Stoklund Olesen2012-02-151-0/+8
| | | | | | | Don't attempt to move instructions with regmask operands. They are most likely calls anyway. llvm-svn: 150634
* Fix library visibility problems with VLIWPacketizer.Andrew Trick2012-02-151-6/+19
| | | | | | The existing framework for postra scheduling is library local. We want to keep it that way. Soon we will have a more general MachineScheduler interface. At that time, various bits will be exposed to targets. In the meantime, the VLIWPacketizer wants to use ScheduleDAGInstrs directly, so it needs to wrapped in a PIMPL to avoid exposing it to the target interface. llvm-svn: 150633
* Make LiveIntervals::handleMove() bundle aware.Lang Hames2012-02-152-4/+16
| | | | llvm-svn: 150630
* Use 'getDataNoRel' for the section kind.Bill Wendling2012-02-151-5/+4
| | | | llvm-svn: 150628
* Fix assertion condition.Lang Hames2012-02-151-1/+1
| | | | llvm-svn: 150627
* Modify the code that emits the module flags to use the new module flags accessorBill Wendling2012-02-152-38/+38
| | | | | | | | | method. This allows the target lowering code to not have to deal with MDNodes. Also, avoid leaking memory like a sieve by not creating a global variable for the image info section, but just emitting the code directly. llvm-svn: 150624
* Don't expose DefaultVLIWSchedulerAndrew Trick2012-02-151-1/+1
| | | | llvm-svn: 150619
* Remove overly conservative assert.Lang Hames2012-02-151-1/+0
| | | | llvm-svn: 150608
* Generic "VLIW" packetizer based on a DFA generated from target itinerary.Andrew Trick2012-02-151-0/+147
| | | | | | Patch by Sundeep! llvm-svn: 150607
* Revert r150565 again. Appears to be a stage2 failure with dragonegg.Andrew Trick2012-02-151-6/+8
| | | | | | I'll put MachineLICM back before PEI. All my arm/x86 benchmarks look good, but buildbots don't like it. llvm-svn: 150568
* Reapply r150565 with the typo fix properly merged.Andrew Trick2012-02-151-8/+6
| | | | llvm-svn: 150567
* reverting r150565. Premature push.Andrew Trick2012-02-151-6/+8
| | | | llvm-svn: 150566
* Move PostRAMachineLICM into MachineLateOptimization. It now runs after PEI!Andrew Trick2012-02-151-8/+6
| | | | llvm-svn: 150565
* Allow CodeGen (llc) command line options to work as expected.Andrew Trick2012-02-151-52/+114
| | | | | | | | | | | | | | | | | | | | | | | | The llc command line options for enabling/disabling passes are local to CodeGen/Passes.cpp. This patch associates those options with standard pass IDs so they work regardless of how the target configures the passes. A target has two ways of overriding standard passes: 1) Redefine the pass pipeline (override TargetPassConfig::add%Stage) 2) Replace or suppress individiual passes with TargetPassConfig::substitutePass. In both cases, the command line options associated with the pass override the target default. For example, say a target wants to disable machine instruction scheduling by default: - The target calls disablePass(MachineSchedulerID) but otherwise does not override any TargetPassConfig methods. - Without any llc options, no scheduler is run. - With -enable-misched, the standard machine scheduler is run and honors the -misched=... flag to select the scheduler variant, which may be used for performance evaluation or testing. Sorry overridePass is ugly. I haven't thought of a better way without replacing the cl::opt framework. I hope to do that one day... I haven't figured out why CodeGen uses char& for pass IDs. AnalysisID is much easier to use and less bug prone. I'm using it wherever I can for internal implementation. Maybe later we can change the global pass ID definitions as well. llvm-svn: 150563
* Added TargetPassConfig::disablePass/substitutePass as a general mechanism to ↵Andrew Trick2012-02-151-6/+42
| | | | | | override specific passes. llvm-svn: 150562
* Don't emit live ranges for physregs live-ins that are dead.Lang Hames2012-02-151-2/+3
| | | | llvm-svn: 150553
* Disentangle moving a machine instr from updating LiveIntervals.Lang Hames2012-02-152-13/+9
| | | | llvm-svn: 150552
* Added hook to let targets custom lower splitting of illegal vectorsPete Cooper2012-02-151-0/+4
| | | | llvm-svn: 150550
* Fix global live range splitting regmask accuracy.Jakob Stoklund Olesen2012-02-141-1/+2
| | | | | | | | Pretend that regmask interference ends at the 'dead' slot, even when there is other interference ending at the 'reg' slot of the same instruction. llvm-svn: 150531
* Fix details in local live range splitting with regmasks.Jakob Stoklund Olesen2012-02-141-6/+16
| | | | | | | Perform all comparisons at instruction granularity, and make sure register masks on uses count in both gaps. llvm-svn: 150530
* Handle regmasks in findRegisterDefOperandIdx().Jakob Stoklund Olesen2012-02-141-0/+4
| | | | | | | | | | | Only accept register masks when looking for an 'overlapping' def. When Overlap is not set, the function searches for a proper definition of Reg. This means MI->modifiesRegister() considers register masks, but MI->definesRegister() doesn't. llvm-svn: 150529
* Use the proper clobber check in handleLiveInRegister().Jakob Stoklund Olesen2012-02-141-1/+1
| | | | | | | | | | | | When a physreg is live in to a basic block, look for any instruction in the block that clobbers the physreg. The instruction doesn't have to properly redefine the register, any overlapping clobber is OK. This slightly changes live ranges when compiling with register masks. llvm-svn: 150528
* Dump live intervals in numerical order.Jakob Stoklund Olesen2012-02-141-4/+15
| | | | | | The old DenseMap hashed order was very confusing. llvm-svn: 150527
* Don't create a new copy of reserved regs - we already have one handy.Lang Hames2012-02-141-4/+2
| | | | llvm-svn: 150525
* Add code to the target lowering object file module to handle module flags.Bill Wendling2012-02-142-0/+64
| | | | | | | | The MachO back-end needs to emit the garbage collection flags specified in the module flags. This is a WIP, so the front-end hasn't been modified to emit these flags just yet. Documentation and front-end switching to occur soon. llvm-svn: 150507
* Update MachineVerifier to check the new physreg live-in rules.Lang Hames2012-02-141-0/+22
| | | | llvm-svn: 150496
* Tighten physical register invariants: Allocatable physical registers canLang Hames2012-02-141-9/+43
| | | | | | only be live in to a block if it is the function entry point or a landing pad. llvm-svn: 150494
* Fix PR12000. Some vector operations may use scalar operands with typesNadav Rotem2012-02-141-1/+5
| | | | | | | | that are greater than the vector element type. For example BUILD_VECTOR of type <1 x i1> with a constant i8 operand. This patch fixes the assertion. llvm-svn: 150477
* Turn push_back loops into append/insert.Benjamin Kramer2012-02-141-4/+2
| | | | llvm-svn: 150471
* Rename getExceptionAddressRegister() to getExceptionPointerRegister() for ↵Lang Hames2012-02-143-3/+3
| | | | | | consistency with setExceptionPointerRegister(...). llvm-svn: 150460
* Use convenience function for consistency.Lang Hames2012-02-141-2/+1
| | | | llvm-svn: 150457
* Don't reserve the R0 and R1 registers here. We don't use these registers, andBill Wendling2012-02-131-0/+6
| | | | | | | marking them as "live-in" into a BB ruins some invariants that the back-end tries to maintain. llvm-svn: 150437
* Don't recalculate the size of the vector each time through the loop.Bill Wendling2012-02-131-2/+2
| | | | llvm-svn: 150436
* Add register mask support to ScheduleDAGRRList.Jakob Stoklund Olesen2012-02-131-11/+49
| | | | | | | | | The scheduler will sometimes check the implicit-def list on instructions to properly handle pre-colored DAG edges. Also check any register mask operands for physreg clobbers. llvm-svn: 150428
* LiveIntervalAnalysis does not depend on MachineLoopInfo.Andrew Trick2012-02-131-4/+2
| | | | llvm-svn: 150411
* Check regmask interference for -join-physregs.Jakob Stoklund Olesen2012-02-131-0/+8
| | | | llvm-svn: 150404
* Fix a bug in DAGCombine for the optimization of BUILD_VECTOR. We cant ↵Nadav Rotem2012-02-131-2/+6
| | | | | | generate a shuffle node from two vectors of different types. llvm-svn: 150383
* This patch addresses the problem of poor code generation for the zextNadav Rotem2012-02-121-14/+29
| | | | | | | | | | | | | | | | | | | v8i8 -> v8i32 on AVX machines. The codegen often scalarizes ANY_EXTEND nodes. The DAGCombiner has two optimizations that can mitigate the problem. First, if all of the operands of a BUILD_VECTOR node are extracted from an ZEXT/ANYEXT nodes, then it is possible to create a new simplified BUILD_VECTOR which uses UNDEFS/ZERO values to eliminate the scalar ZEXT/ANYEXT nodes. Second, another dag combine optimization lowers BUILD_VECTOR into a shuffle vector instruction. In the case of zext v8i8->v8i32 on AVX, a value in an XMM register is to be shuffled into a wide YMM register. This patch modifes the second optimization and allows the creation of shuffle vectors even when the newly generated vector and the original vector from which we extract the values are of different types. llvm-svn: 150340
* Add support for implicit TLS model used with MS VC runtime.Anton Korobeynikov2012-02-111-1/+10
| | | | | | Patch by Kai Nacke! llvm-svn: 150307
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