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* fix what looks like a real logic bug, found by PVS-Studio (part of PR12357)Chris Lattner2012-03-271-2/+2
| | | | llvm-svn: 153513
* Add an MRI::tracksLiveness() flag.Jakob Stoklund Olesen2012-03-272-1/+6
| | | | | | | | | | | | | | | | | | | | Late optimization passes like branch folding and tail duplication can transform the machine code in a way that makes it expensive to keep the register liveness information up to date. There is a fuzzy line between register allocation and late scheduling where the liveness information degrades. The MRI::tracksLiveness() flag makes the line clear: While true, liveness information is accurate, and can be used for register scavenging. Once the flag is false, liveness information is not accurate, and can only be used as a hint. Late passes generally don't need the liveness information, but they will sometimes use the register scavenger to help update it. The scavenger enforces strict correctness, and we have to spend a lot of code to update register liveness that may never be used. llvm-svn: 153511
* Post-ra LICM should take care not to hoist an instruction that would clobber aEvan Cheng2012-03-271-4/+28
| | | | | | | | register that's read by the preheader terminator. rdar://11095580 llvm-svn: 153492
* During MachineCopyPropagation a register may be the source operand of multipleLang Hames2012-03-271-17/+26
| | | | | | | | | | copies being considered for removal. Make sure to track all of the copies, rather than just the most recent encountered, by holding a DenseSet instead of an unsigned in SrcMap. No test case - couldn't reduce something with a sane size. llvm-svn: 153487
* Add a debug option to dump PBQP graphs during register allocation.Lang Hames2012-03-261-0/+29
| | | | llvm-svn: 153483
* Use the file in the inlined die rather than the compile unit forEric Christopher2012-03-261-1/+2
| | | | | | | | | | | | | | backtrace locations. Testcase forthcoming, but I wanted to get some testing here. Should fix: PR12323 PR12314 rdar://11091100 llvm-svn: 153471
* No need to do an expensive stable sort for a bunch of integers.Benjamin Kramer2012-03-261-3/+3
| | | | llvm-svn: 153438
* Prune some includes and forward declarations.Craig Topper2012-03-261-3/+4
| | | | llvm-svn: 153429
* Add a debug statement.Eric Christopher2012-03-261-1/+3
| | | | llvm-svn: 153428
* Add the ability to promote legal integer VAARGs. This is required for the ↵Hal Finkel2012-03-241-1/+33
| | | | | | PPC64 SVR4 ABI. llvm-svn: 153372
* Pretty-printing comments for literal floating point in .s files.Jim Grosbach2012-03-231-2/+6
| | | | | | | Dump the hex representation to the comment stream as well as the float value. llvm-svn: 153346
* Add support for register masks to PBQP.Lang Hames2012-03-231-4/+38
| | | | llvm-svn: 153341
* Source order scheduler should not preschedule nodes with multiple uses. ↵Evan Cheng2012-03-221-7/+11
| | | | | | rdar://11096639 llvm-svn: 153270
* Assign node orders to target intrinsics which do not produce results. ↵Evan Cheng2012-03-221-0/+6
| | | | | | rdar://11096639 llvm-svn: 153269
* In erroneous inline assembly we could mistakenly try to access theEric Christopher2012-03-221-1/+5
| | | | | | | | | metadata operand as an actual operand, leading to an assert. Error out in this case. rdar://11007633 llvm-svn: 153234
* [fast-isel] Fold "urem x, pow2" -> "and x, pow2-1". This should fix the 271%Chad Rosier2012-03-221-0/+7
| | | | | | | | | execution-time regression for nsieve-bits on the ARMv7 -O0 -g nightly tester. This may also improve compile-time on architectures that would otherwise generate a libcall for urem (e.g., ARM) or fall back to the DAG selector. rdar://10810716 llvm-svn: 153230
* Checking a build_vector for an all-ones value.Jim Grosbach2012-03-211-5/+14
| | | | | | | | Type legalization can zero-extend the elements of the build_vector node, so, for example, we may have an <8 x i8> with i32 elements of value 255. That should return 'true' for the vector being all ones. llvm-svn: 153203
* misched: fix LiveInterval update for bottom-up schedulingAndrew Trick2012-03-211-3/+13
| | | | llvm-svn: 153162
* misched: trace LiveIntervals after scheduling.Andrew Trick2012-03-211-0/+1
| | | | llvm-svn: 153161
* misched: obvious iterator update fixes for bottom-up.Andrew Trick2012-03-211-0/+6
| | | | llvm-svn: 153160
* misched: cleanup main loopAndrew Trick2012-03-211-10/+14
| | | | llvm-svn: 153159
* misched: fix LI update for bottom-up.Andrew Trick2012-03-211-1/+7
| | | | llvm-svn: 153158
* It's possible to have a constant expression who's size is quite big (e.g.,Bill Wendling2012-03-201-11/+17
| | | | | | | | | | | | | | i128). In that case, we may not be able to print out the MCExpr as an expression. For instance, we could have an MCExpr like this: 0xBEEF0000BEEF0000 | (0xBEEF0000BEEF0000 << 64) The MCExpr printer handles sizes up to 64-bits, but this expression would require 128-bits. In this situation, try to evaluate the constant expression and emit that as the value into 64-bit chunks. <rdar://problem/11070338> llvm-svn: 153081
* When combining (vextract shuffle (load ), <1,u,u,u>), 0) -> (load ), add ↵Craig Topper2012-03-201-0/+1
| | | | | | users of the final load to the worklist too. Needed by changes I'm preparing to make to X86 backend. llvm-svn: 153078
* Do everything up to generating code to try to get a register forEric Christopher2012-03-201-1/+6
| | | | | | | | | | a variable. The previous code would break the debug info changing code invariant. This will regress debug info for arguments where we elide the alloca created. Fixes rdar://11066468 llvm-svn: 153074
* Untabify.Eric Christopher2012-03-201-2/+2
| | | | llvm-svn: 153073
* Add another debugging statement here.Eric Christopher2012-03-201-0/+4
| | | | llvm-svn: 153072
* Use lookUpRegForValue here instead of duplicating the code.Eric Christopher2012-03-201-9/+2
| | | | llvm-svn: 153071
* f16 FDIV can now be legalized by promoting to f32Pete Cooper2012-03-191-1/+2
| | | | llvm-svn: 153064
* Add an option to the MI scheduler to cut off scheduling after a fixed number ofLang Hames2012-03-191-1/+19
| | | | | | | instructions have been scheduled. Handy for tracking down scheduler bugs, or bugs exposed by scheduling. llvm-svn: 153045
* Fix DAG combine which creates illegal vector shuffles. Patch by Heikki Kultala.Duncan Sands2012-03-191-0/+6
| | | | llvm-svn: 153035
* CriticalAntiDepBreaker: Replace a SmallSet of regs with a much denser BitVector.Benjamin Kramer2012-03-172-11/+12
| | | | llvm-svn: 152999
* MachineInstr: Inline the fast path (non-bundle instruction) of hasProperty.Benjamin Kramer2012-03-171-6/+2
| | | | | | This is particularly helpful as both arguments tend to be constants. llvm-svn: 152991
* ScheduleDAGInstrs: When adding uses we add them into a set that's empty at ↵Benjamin Kramer2012-03-161-2/+2
| | | | | | the beginning, no need to maintain another set for the added regs. llvm-svn: 152934
* Limit the number of memory operands in MachineInstr to 2^16 and store the ↵Benjamin Kramer2012-03-161-11/+10
| | | | | | | | number in padding. Saves one machine word on MachineInstr (88->80 bytes on x86_64, 48->44 on i386). llvm-svn: 152930
* CriticalAntiDepBreaker: BasicBlock::size is an expensive operation, reuse ↵Benjamin Kramer2012-03-161-7/+7
| | | | | | | | the cached value. No functionality change. llvm-svn: 152927
* misched: add DAG edges from vreg defs to ExitSU.Andrew Trick2012-03-161-1/+3
| | | | | | | | | | These edges are not really necessary, but it is consistent with the way we currently create physreg edges. Scheduler heuristics that expect a DAG edge to the block terminator could benefit from this change. Although in the future I hope we have a better mechanism for modeling latency across scheduling regions. llvm-svn: 152895
* Revert r152705, which reapplied r152486 as this appears to be causing failuresChad Rosier2012-03-161-128/+34
| | | | | | | | | | | on our internal nightly testers. So, basically revert r152486 again. Abbreviated original commit message: Implement a more intelligent way of spilling uses across an invoke boundary. It looks as if Chander's inlining work, r152737, exposed an issue. llvm-svn: 152887
* Revert r152613 (and r152614), "Inline the d'tor and add an anchor instead." ↵NAKAMURA Takumi2012-03-161-1/+1
| | | | | | | | | for workaround of g++-4.4's miscompilation. It caused MSP430DAGToDAGISel::SelectIndexedBinOp() to be miscompiled. When two ReplaceUses()'s are expanded as inline, vtable in base class is stored to latter (ISelUpdater)ISU. llvm-svn: 152877
* For types with a parent of the compile unit make sure and emitEric Christopher2012-03-151-5/+4
| | | | | | | | the DECL information. rdar://10855921 llvm-svn: 152876
* We actually handle AllocaInst via getRegForValue below just fine.Eric Christopher2012-03-151-1/+1
| | | | | | Part of rdar://8905263 llvm-svn: 152845
* Add some debugging output into fast isel as well.Eric Christopher2012-03-151-2/+6
| | | | llvm-svn: 152844
* Add another debug statement.Eric Christopher2012-03-151-1/+3
| | | | llvm-svn: 152843
* Tabs.Eric Christopher2012-03-151-3/+3
| | | | llvm-svn: 152842
* Typo.Eric Christopher2012-03-151-1/+1
| | | | llvm-svn: 152841
* When optimizing certain BUILD_VECTOR nodes into other BUILD_VECTOR nodes, ↵Nadav Rotem2012-03-151-0/+4
| | | | | | add the new node into the work list because there is a potential for further optimizations. llvm-svn: 152784
* Revert the removal of DW_AT_MIPS_linkage_name when we aren't puttingEric Christopher2012-03-151-5/+8
| | | | | | | | | out the DW_AT_name. Older gdbs unfortunately still use it to disambiguate member functions in templated classes (gdb.cp/templates.exp). rdar://11043421 (which is now deferred for a bit) llvm-svn: 152782
* Add a xform to the DAG combiner.Bill Wendling2012-03-151-0/+17
| | | | | | | | | | | | Transform: (fsub x, (fadd x, y)) -> (fneg y) and (fsub x, (fadd y, x)) -> (fneg y) if 'unsafe math' is specified. <rdar://problem/7540295> llvm-svn: 152777
* Silence operator precedence warnings.Benjamin Kramer2012-03-141-3/+3
| | | | llvm-svn: 152711
* Reapply r152486 with a fix for the nightly testers.Bill Wendling2012-03-141-34/+128
| | | | | | | | | There were cases where a value could be used and it's both crossing an invoke and NOT crossing an invoke. This could happen in the landing pads. In that case, we will demote the value to the stack like we did before. <rdar://problem/10609139> llvm-svn: 152705
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