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* Handle PHI nodes prefacing EH pads tooDavid Majnemer2015-08-061-13/+87
| | | | llvm-svn: 244274
* handle phi nodesDavid Majnemer2015-08-061-4/+27
| | | | llvm-svn: 244273
* [WinEHPrepare] Add rudimentary support for the new EH instructionsDavid Majnemer2015-08-061-8/+301
| | | | | | | | | | | | | | | | | | | | | | | Summary: This adds somewhat basic preparation functionality including: - Formation of funclets via coloring basic blocks. - Cloning of polychromatic blocks to ensure that funclets have unique program counters. - Demotion of values used between different funclets. - Some amount of cleanup once we have removed predecessors from basic blocks. - Verification that we are left with a CFG that makes some amount of sense. N.B. Arguments and numbering still need to be done. Reviewers: rnk, JosephTremoulet Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11750 llvm-svn: 244272
* Rename inst_range() to instructions() for consistency. NFCNico Rieck2015-08-061-1/+1
| | | | llvm-svn: 244248
* Fix possible infinite loop in shrink wrapping when searching for save/restoreKit Barton2015-08-061-6/+24
| | | | | | | | | | | | | | | | | | | | points. There is an infinite loop that can occur in Shrink Wrapping while searching for the Save/Restore points. Part of this search checks whether the save/restore points are located in different loop nests and if so, uses the (post) dominator trees to find the immediate (post) dominator blocks. However, if the current block does not have any immediate (post) dominators then this search will result in an infinite loop. This can occur in code containing an infinite loop. The modification checks whether the immediate (post) dominator is different from the current save/restore block. If it is not, then the search terminates and the current location is not considered as a valid save/restore point for shrink wrapping. Phabricator: http://reviews.llvm.org/D11607 llvm-svn: 244247
* MIR Parser: Report an error when parsing duplicate memory operand flags.Alex Lorenz2015-08-061-1/+5
| | | | llvm-svn: 244240
* Revert r244154 which causes some build failure. See ↵Cong Hou2015-08-064-61/+40
| | | | | | https://llvm.org/bugs/show_bug.cgi?id=24377. llvm-svn: 244239
* This patch changes the interface to enable the shrink wrapping optimization. Kit Barton2015-08-062-22/+50
| | | | | | | | | | | | | | | It adds a new constructor, which takes a std::function predicate function that is run at the beginning of shrink wrapping to determine whether the optimization should run on the given machine function. The std::function can be overridden by each target, allowing target-specific decisions to be made on each machine function. This is necessary for PowerPC, as the decision to run shrink wrapping is partially based on the ABI. Futhermore, this operates nicely with the GCC iFunc capability, which allows option overrides on a per-function basis. Phabricator: http://reviews.llvm.org/D11421 llvm-svn: 244235
* MIR Serialization: Serialize the 'invariant' machine memory operand flag.Alex Lorenz2015-08-064-3/+11
| | | | llvm-svn: 244230
* Fix an alignment error in `llvm::expandAtomicRMWToCmpXchg` without breaking ↵Richard Diamond2015-08-061-1/+1
| | | | | | | | | | | | | | the build where X86 isn't enabled. Summary: Divide the primitive size in bits by eight so the initial load's alignment is in bytes as expected. Tested with the included unit test. Reviewers: rengolin, jfb Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11804 llvm-svn: 244229
* MIR Serialization: Serialize the 'non-temporal' machine memory operand flag.Alex Lorenz2015-08-064-1/+10
| | | | llvm-svn: 244228
* Revert "Divide the primitive size in bits by eight so the initial load's ↵Renato Golin2015-08-061-1/+1
| | | | | | | | | alignment is in bytes as expected. Tested with the included unit test." This reverts commit r244155, as it was breaking the buildbots for too long. Should be reapplied with proper fix. llvm-svn: 244205
* [PM/AA] Hoist the interface for BasicAA into a header file.Chandler Carruth2015-08-061-0/+1
| | | | | | | | | | | | | This is the first mechanical step in preparation for making this and all the other alias analysis passes available to the new pass manager. I'm factoring out all the totally boring changes I can so I'm moving code around here with no other changes. I've even minimized the formatting churn. I'll reformat and freshen comments on the interface now that its located in the right place so that the substantive changes don't triger this. llvm-svn: 244197
* [PM/AA] Simplify the AliasAnalysis interface by removing a wrapperChandler Carruth2015-08-061-5/+7
| | | | | | | | | | | | | | | | around a DataLayout interface in favor of directly querying DataLayout. This wrapper specifically helped handle the case where this no DataLayout, but LLVM now requires it simplifynig all of this. I've updated callers to directly query DataLayout. This in turn exposed a bunch of places where we should have DataLayout readily available but don't which I've fixed. This then in turn exposed that we were passing DataLayout around in a bunch of arguments rather than making it readily available so I've also fixed that. No functionality changed. llvm-svn: 244189
* MIR Serialization: Initial serialization of the machine operand target flags.Alex Lorenz2015-08-064-13/+91
| | | | | | | | | | | | This commit implements the initial serialization of the machine operand target flags. It extends the 'TargetInstrInfo' class to add two new methods that help to provide text based serialization for the target flags. This commit can serialize only the X86 target flags, and the target flags for the other targets will be serialized in the follow-up commits. Reviewers: Duncan P. N. Exon Smith llvm-svn: 244185
* If the "CodeView" module flag is set, emit codeview instead of DWARFReid Kleckner2015-08-052-12/+5
| | | | | | | | | | | | | | Summary: Emit both DWARF and CodeView if "CodeView" and "Dwarf Version" module flags are set. Reviewers: majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11756 llvm-svn: 244158
* MIR Serialization: Serialize the machine operand's offset.Alex Lorenz2015-08-054-9/+60
| | | | | | | This commit serializes the offset for the following operands: target index, global address, external symbol, constant pool index, and block address. llvm-svn: 244157
* Divide the primitive size in bits by eight so the initial load's alignment is inRichard Diamond2015-08-051-1/+1
| | | | | | bytes as expected. Tested with the included unit test. llvm-svn: 244155
* Record whether the weights on out-edges from a MBB are normalized.Cong Hou2015-08-054-40/+61
| | | | | | | | | | | | 1. Create a utility function normalizeEdgeWeights() in MachineBranchProbabilityInfo that normalizes a list of edge weights so that the sum of then can fit in uint32_t. 2. Provide an interface in MachineBasicBlock to normalize its successors' weights. 3. Add a flag in MachineBasicBlock that tracks whether its successors' weights are normalized. 4. Provide an overload of getSumForBlock that accepts a non-const pointer to a MBB so that it can force normalizing this MBB's successors' weights. 5. Update several uses of getSumForBlock() by eliminating the once needed weight scale. Differential Revision: http://reviews.llvm.org/D11442 llvm-svn: 244154
* Revert "Fix MO's analyzePhysReg, it was confusing sub- and super-registers. ↵JF Bastien2015-08-051-1/+1
| | | | | | | | Problem pointed out by Michael Hordijk." I mistakenly committed the patch for D6629, and was trying to commit another. Reverting until it gets proper signoff. llvm-svn: 244121
* Fix MO's analyzePhysReg, it was confusing sub- and super-registers. Problem ↵JF Bastien2015-08-051-1/+1
| | | | | | pointed out by Michael Hordijk. llvm-svn: 244120
* Write access test.Richard Diamond2015-08-051-1/+2
| | | | llvm-svn: 244103
* MIR Parser: Report an error when parsing large immediate operands.Alex Lorenz2015-08-051-2/+1
| | | | llvm-svn: 244100
* MIR Serialization: Serialize the typed immediate integer machine operands.Alex Lorenz2015-08-054-0/+33
| | | | llvm-svn: 244098
* MIR Parser: Extract the IR constant parsing code into a new method. NFC.Alex Lorenz2015-08-051-7/+14
| | | | | | | | This commit extracts the code that parses the IR constant values into a new method named 'parseIRConstant' in the 'MIParser' class. The new method will be reused by the code that parses the typed integer immediate machine operands. llvm-svn: 244093
* MIR Parser: Report an error when parsing duplicate register flags.Alex Lorenz2015-08-051-1/+5
| | | | llvm-svn: 244081
* [TTI] Make the cost APIs in TargetTransformInfo consistently use 'int'Chandler Carruth2015-08-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | rather than 'unsigned' for their costs. For something like costs in particular there is a natural "negative" value, that of savings or saved cost. As a consequence, there is a lot of code that subtracts or creates negative values based on cost, all of which is prone to awkwardness or bugs when dealing with an unsigned type. Similarly, we *never* want these values to wrap, as that would cause Very Bad code generation (likely percieved as an infinite loop as we try to emit over 2^32 instructions or some such insanity). All around 'int' seems a much better fit for these basic metrics. I've added asserts to ensure that at least the TTI interface never returns negative numbers here. If we ever have a use case for negative numbers, we can remove this, but this way a bug where someone used '-1' to produce a 'very large' cost will be caught by the assert. This passes all tests, and is also UBSan clean. No functional change intended. Differential Revision: http://reviews.llvm.org/D11741 llvm-svn: 244080
* MIR Serialization: Serialize the 'early-clobber' register operand flag.Alex Lorenz2015-08-054-2/+10
| | | | llvm-svn: 244075
* MIR Serialization: Serialize the 'debug-use' register operand flag.Alex Lorenz2015-08-054-2/+11
| | | | llvm-svn: 244071
* MIR Parser: Simplify the handling of quoted tokens. NFC.Alex Lorenz2015-08-053-77/+42
| | | | | | | The machine instructions lexer should not expose the difference between quoted and unquoted tokens to the parser. llvm-svn: 244068
* revert r243687: enable fast-math-flag propagation to DAG nodes Sanjay Patel2015-08-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can't propagate FMF partially without breaking DAG-level CSE. We either need to relax CSE to account for mismatched FMF as a temporary work-around or fully propagate FMF throughout the DAG. Surprisingly, there are no existing regression tests for this, but here's an example: define float @fmf(float %a, float %b) { %mul1 = fmul fast float %a, %b %nega = fsub fast float 0.0, %a %mul2 = fmul fast float %nega, %b %abx2 = fsub fast float %mul1, %mul2 ret float %abx2 } $ llc -o - badflags.ll -march=x86-64 -mattr=fma -enable-unsafe-fp-math -enable-fmf-dag=0 ... vmulss %xmm1, %xmm0, %xmm0 vaddss %xmm0, %xmm0, %xmm0 retq $ llc -o - badflags.ll -march=x86-64 -mattr=fma -enable-unsafe-fp-math -enable-fmf-dag=1 ... vmulss %xmm1, %xmm0, %xmm2 vfmadd213ss %xmm2, %xmm1, %xmm0 <--- failed to recognize that (a * b) was already calculated retq llvm-svn: 244053
* [MachineCombiner] Don't use the opcode-only form of computeInstrLatencyHal Finkel2015-08-051-1/+1
| | | | | | | | | In r242277, I updated the MachineCombiner to work with itineraries, but I missed a call that is scheduling-model-only (the opcode-only form of computeInstrLatency). Using the form that takes an MI* allows this to work with itineraries (and should be NFC for subtargets with scheduling models). llvm-svn: 244020
* wrap OptSize and MinSize attributes for easier and consistent access (NFCI)Sanjay Patel2015-08-049-9/+10
| | | | | | | | | | | | | | | | | Create wrapper methods in the Function class for the OptimizeForSize and MinSize attributes. We want to hide the logic of "or'ing" them together when optimizing just for size (-Os). Currently, we are not consistent about this and rely on a front-end to always set OptimizeForSize (-Os) if MinSize (-Oz) is on. Thus, there are 18 FIXME changes here that should be added as follow-on patches with regression tests. This patch is NFC-intended: it just replaces existing direct accesses of the attributes by the equivalent wrapper call. Differential Revision: http://reviews.llvm.org/D11734 llvm-svn: 243994
* [SDAG] Fix a result chain in ExpandUnalignedLoadHal Finkel2015-08-041-1/+1
| | | | | | | | | | | | On the code path in ExpandUnalignedLoad which expands an unaligned vector/fp value in terms of a legal integer load of the same size, the ChainResult needs to be the chain result of the integer load. No in-tree test case is currently available. Patch by Jan Hranac! llvm-svn: 243956
* Introduce enum value for previously defined metadata -- make.implicit Chen Li2015-08-041-1/+2
| | | | | | | | | | | | Summary: This patch adds enum value for an existing metadata type -- make.implicit. Using preassigned enum will be helpful to get compile time type checking and avoid string construction and comparison. The patch also changes uses of make.implicit from string metadata to enum metadata. There is no functionality change. Reviewers: reames Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11698 llvm-svn: 243954
* [CodeGen] Fix FCOPYSIGN legalization to account for mismatched types.Ahmed Bougacha2015-08-042-2/+53
| | | | | | | | | | | | | | We used to legalize it like it's any other binary operations. It's not, because it accepts mismatched operand types. Because of that, we used to hit various asserts and miscompiles. Specialize vector legalizations to, in the worst case, unroll, or, when possible, to just legalize the operand that needs legalization. Scalarization isn't covered, because I can't think of a target where some but not all of the 1-element vector types are to be scalarized. llvm-svn: 243924
* MIR Serialization: Serialize the 'volatile' machine memory operand flag.Alex Lorenz2015-08-044-2/+26
| | | | llvm-svn: 243923
* MIR Serialization: Initial serialization of the machine memory operands.Alex Lorenz2015-08-034-7/+173
| | | | | Reviewers: Duncan P. N. Exon Smith llvm-svn: 243915
* -Wdeprecated-clean: Fix cases of violating the rule of 5 in ways that are ↵David Blaikie2015-08-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | deprecated in C++11 Various value handles needed to be copy constructible and copy assignable (mostly for their use in DenseMap). But to avoid an API that might allow accidental slicing, make these members protected in the base class and make derived classes final (the special members become implicitly public there - but disallowing further derived classes that might be sliced to the intermediate type). Might be worth having a warning a bit like -Wnon-virtual-dtor that catches public move/copy assign/ctors in classes with virtual functions. (suppressable in the same way - by making them protected in the base, and making the derived classes final) Could be fancier and only diagnose them when they're actually called, potentially. Also allow a few default implementations where custom implementations (especially with non-standard return types) were implemented. llvm-svn: 243909
* -Wdeprecated-clean: Fix cases of violating the rule of 5 in ways that are ↵David Blaikie2015-08-031-5/+8
| | | | | | | | | | deprecated in C++11 Some functions return concrete ByteStreamers by value - explicitly support that in the base class. (dtor can be virtual, no one seems to be polymorphically owning/destroying them) llvm-svn: 243897
* Refactor AtomicExpand::expandAtomicRMWToCmpXchg into a standalone function.JF Bastien2015-08-031-66/+82
| | | | | | | | | | | | | | | Summary: This is useful for PNaCl's `RewriteAtomics` pass. NaCl intrinsics don't exist for some of the more exotic RMW instructions, so by refactoring this function into its own, `RewriteAtomics` can share code rewriting those atomics with `AtomicExpand` while additionally saving a few cycles by generating the `cmpxchg` NaCl-specific intrinsic with the callback. Without this patch, `RewriteAtomics` would require two extra passes over functions, by first requiring use of the full `AtomicExpand` pass to just expand the leftover exotic RMWs and then running itself again to expand resulting `cmpxchg`s. NFC Reviewers: jfb Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D11422 llvm-svn: 243880
* [GlobalMerge] Allow targets to enable merging of extern variables, NFC.John Brawn2015-08-031-8/+15
| | | | | | | | | | Adjust the GlobalMergeOnExternal option so that the default behaviour is to do whatever the Target thinks is best. Explicitly enabled or disabling the option will override this default. Differential Revision: http://reviews.llvm.org/D10965 llvm-svn: 243873
* AsmPrinter: Split out non-DIE printing from DIE::print(), NFCDuncan P. N. Exon Smith2015-08-021-28/+24
| | | | | | | | Split out a helper `printValues()` for printing `DIEBlock` and `DIELoc`, instead of relying on `DIE::print()`. The shared code was actually fairly small there. No functionality change intended. llvm-svn: 243856
* AsmPrinter: Take DIEValueList in some DwarfUnit API, NFCDuncan P. N. Exon Smith2015-08-022-13/+17
| | | | | | | Take `DIEValueList` instead of `DIE` so that `DIEBlock` and `DIELoc` can stop inheriting from `DIE` in a future commit. llvm-svn: 243855
* AsmPrinter: Change DIEValueList to a subclass of DIE, NFCDuncan P. N. Exon Smith2015-08-021-6/+6
| | | | | | | | | | | | | | | Rewrite `DIEValueList` as a subclass of `DIE`, renaming its API to match `DIE`'s. This is preparation for changing `DIEBlock` and `DIELoc` to stop inheriting from `DIE` and inherit directly from `DIEValueList`. I thought about leaving this as a has-a relationship (and changing `DIELoc` and `DIEBlock` to also have-a `DIEValueList`), but that seemed to require a fair bit more boilerplate and I think it needed more changes to the `DwarfUnit` API than this will. No functionality change intended here. llvm-svn: 243854
* Remove trailing whitespace. NFCI.Simon Pilgrim2015-08-011-7/+7
| | | | llvm-svn: 243838
* Use SDValue bool check. NFCI.Simon Pilgrim2015-08-011-20/+10
| | | | llvm-svn: 243837
* [DAGCombiner] Convert constant AND masks to shuffle clear masks down to the ↵Simon Pilgrim2015-08-011-21/+64
| | | | | | | | | | | | | | byte level The XformToShuffleWithZero method currently checks AND masks at the per-lane level for all-one and all-zero constants and attempts to convert them to legal shuffle clear masks. This patch generalises XformToShuffleWithZero, splitting and checking the sub-lanes of the constants down to the byte level to see if any legal shuffle clear masks are possible. This allows a lot of masks (often from legalization or truncation) to be folded into existing shuffle patterns and removes a lot of constant mask loading. There are a few examples of poor shuffle lowering that are exposed by this patch that will be cleaned up in future patches (e.g. merging shuffles that are separated by bitcasts, x86 legalized v8i8 zero extension uses PMOVZX+AND+AND instead of AND+PMOVZX, etc.) Differential Revision: http://reviews.llvm.org/D11518 llvm-svn: 243831
* MIR Parser: Report an error when a jump table entry is redefined.Alex Lorenz2015-07-311-2/+5
| | | | llvm-svn: 243798
* MIR Parser: Remove unused variable.Alex Lorenz2015-07-311-1/+0
| | | | | | This variable is unused as of r243572. llvm-svn: 243796
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