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* Unconditionally create a new MCInstrInfo in the asm printer forEric Christopher2015-02-211-5/+4
| | | | | | | | asm parsing since it's not subtarget dependent and we can't depend upon the one hanging off the MachineFunction's subtarget still being around. llvm-svn: 230135
* X86: Call __main using the SelectionDAGDavid Majnemer2015-02-211-1/+0
| | | | | | | | Synthesizing a call directly using the MI layer would confuse the frame lowering code. This is problematic as frame lowering is highly sensitive the particularities of calls, etc. llvm-svn: 230129
* LiveRangeCalc: Don't start liveranges of PHI instruction at the block begin.Matthias Braun2015-02-201-5/+2
| | | | | | | | | | | | | | | | | | Summary: Letting them begin at the PHI instruction slightly simplifies the code but more importantly avoids breaking the assumption that live ranges starting at the block begin are also live at the end of the predecessor blocks. The MachineVerifier checks that but was apparently never run in the few instances where liveranges are calculated for machine-SSA functions. Reviewers: qcolombet Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7779 llvm-svn: 230093
* Use short names for jumptable sections.Rafael Espindola2015-02-201-29/+25
| | | | | | Also refactor code to remove some duplication. llvm-svn: 230087
* Used the cached subtarget off of the MachineFunction.Eric Christopher2015-02-202-5/+3
| | | | llvm-svn: 230078
* Add generic fmad DAG node.Matt Arsenault2015-02-204-95/+164
| | | | | | | | | | | This allows sharing of FMA forming combines to work with instructions that have the same semantics as a separate multiply and add. This is expand by default, and only formed post legalization so it shouldn't have much impact on targets that do not want it. llvm-svn: 230070
* Grab the DataLayout off of the TargetMachine since that's whereEric Christopher2015-02-201-2/+2
| | | | | | it's stored. llvm-svn: 230059
* Get the function specific subtarget.Eric Christopher2015-02-201-1/+2
| | | | llvm-svn: 230038
* Get the cached subtarget off the MachineFunction rather thanEric Christopher2015-02-201-4/+2
| | | | | | inquiring for a new one from the TargetMachine. llvm-svn: 230037
* Generalize statepoint lowering to use ImmutableStatepoint. Move statepoint ↵Igor Laevsky2015-02-202-40/+41
| | | | | | | | lowering into a separate function 'LowerStatepoint' which uses ImmutableStatepoint instead of a CallInst. Also related utility functions are changed to receive ImmutableCallSite. Differential Revision: http://reviews.llvm.org/D7756 llvm-svn: 230017
* Fix build with gcc. This has a -Wsequence-point error on 'MII', which is a ↵Nick Lewycky2015-02-201-5/+3
| | | | | | good point. llvm-svn: 229979
* Remove more uses of TargetMachine::getSubtargetImpl from theEric Christopher2015-02-201-9/+8
| | | | | | | | | | AsmPrinter. getSubtargetInfo now asserts that the MachineFunction exists. Debug printing of register naming now uses the register info from MCAsmInfo as that's unchanging. llvm-svn: 229978
* AsmPrinter::doFinalization is at the module level and so doesn'tEric Christopher2015-02-201-2/+7
| | | | | | | have access to a target specific subtarget info. Grab the module level MCSubtargetInfo for the JumpInstrTable output stubs. llvm-svn: 229974
* Remove the MCInstrInfo cached variable as it was only used in aEric Christopher2015-02-202-15/+13
| | | | | | | single place and replace calls to getSubtargetImpl with calls to get the subtarget from the MachineFunction where valid. llvm-svn: 229971
* Revert r229944: EH: Prune unreachable resume instructions during Dwarf EH ↵Chandler Carruth2015-02-203-111/+22
| | | | | | | | | preparation This doesn't pass 'ninja check-llvm' for me. Lots of tests, including the ones updated, fail with crashes and other explosions. llvm-svn: 229952
* EH: Prune unreachable resume instructions during Dwarf EH preparationReid Kleckner2015-02-203-22/+111
| | | | | | | | | | | | | | | | | Today a simple function that only catches exceptions and doesn't run destructor cleanups ends up containing a dead call to _Unwind_Resume (PR20300). We can't remove these dead resume instructions during normal optimization because inlining might introduce additional landingpads that do have cleanups to run. Instead we can do this during EH preparation, which is guaranteed to run after inlining. Fixes PR20300. Reviewers: majnemer Differential Revision: http://reviews.llvm.org/D7744 llvm-svn: 229944
* This needs to be a const variable so the two sides of the ternaryEric Christopher2015-02-201-1/+2
| | | | | | operator agree on type. llvm-svn: 229938
* Only use the initialized MCInstrInfo if it's been initialized alreadyEric Christopher2015-02-191-1/+5
| | | | | | | | during SetupMachineFunction. This is also the single use of MII and it'll be changing to TargetInstrInfo (which is MachineFunction based) in the next commit here. llvm-svn: 229931
* Migrate away a use of the subtarget (and TargetMachine) fromEric Christopher2015-02-191-5/+4
| | | | | | | AsmPrinterDwarf since the information is on the MCRegisterInfo via the MCContext and MMI that we already have on the AsmPrinter. llvm-svn: 229928
* [CodeGen] Use ArrayRef instead of std::vector&. NFC.Ahmed Bougacha2015-02-191-1/+1
| | | | | | The former lets us use SmallVectors. Do so in ARM and AArch64. llvm-svn: 229925
* MCTargetOptions reside on the TargetMachine that we always have viaEric Christopher2015-02-191-5/+2
| | | | | | TargetOptions. llvm-svn: 229917
* Remove a call to TargetMachine::getSubtarget from the inlineEric Christopher2015-02-191-1/+11
| | | | | | | | | asm support in the asm printer. If we can get a subtarget from the machine function then we should do so, otherwise we can go ahead and create a default one since we're at the module level. llvm-svn: 229916
* Remove unused argument from emitInlineAsmStart.Eric Christopher2015-02-191-3/+3
| | | | llvm-svn: 229907
* Update and remove a few calls to TargetMachine::getSubtargetImplEric Christopher2015-02-191-9/+12
| | | | | | out of the asm printer. llvm-svn: 229883
* Demote vectors to arrays. No functionality change.Benjamin Kramer2015-02-191-7/+3
| | | | llvm-svn: 229861
* [x86,sdag] Two interrelated changes to the x86 and sdag code.Chandler Carruth2015-02-191-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First, don't combine bit masking into vector shuffles (even ones the target can handle) once operation legalization has taken place. Custom legalization of vector shuffles may exist for these patterns (making the predicate return true) but that custom legalization may in some cases produce the exact bit math this matches. We only really want to handle this prior to operation legalization. However, the x86 backend, in a fit of awesome, relied on this. What it would do is mark VSELECTs as expand, which would turn them into arithmetic, which this would then match back into vector shuffles, which we would then lower properly. Amazing. Instead, the second change is to teach the x86 backend to directly form vector shuffles from VSELECT nodes with constant conditions, and to mark all of the vector types we support lowering blends as shuffles as custom VSELECT lowering. We still mark the forms which actually support variable blends as *legal* so that the custom lowering is bypassed, and the legal lowering can even be used by the vector shuffle legalization (yes, i know, this is confusing. but that's how the patterns are written). This makes the VSELECT lowering much more sensible, and in fact should fix a bunch of bugs with it. However, as you'll see in the test cases, right now what it does is point out the *hilarious* deficiency of the new vector shuffle lowering when it comes to blends. Fortunately, my very next patch fixes that. I can't submit it yet, because that patch, somewhat obviously, forms the exact and/or pattern that the DAG combine is matching here! Without this patch, teaching the vector shuffle lowering to produce the right code infloops in the DAG combiner. With this patch alone, we produce terrible code but at least lower through the right paths. With both patches, all the regressions here should be fixed, and a bunch of the improvements (like using 2 shufps with no memory loads instead of 2 andps with memory loads and an orps) will stay. Win! There is one other change worth noting here. We had hilariously wrong vectorization cost estimates for vselect because we fell through to the code path that assumed all "expand" vector operations are scalarized. However, the "expand" lowering of VSELECT is vector bit math, most definitely not scalarized. So now we go back to the correct if horribly naive cost of "1" for "not scalarized". If anyone wants to add actual modeling of shuffle costs, that would be cool, but this seems an improvement on its own. Note the removal of 16 and 32 "costs" for doing a blend. Even in SSE2 we can blend in fewer than 16 instructions. ;] Of course, we don't right now because of OMG bad code, but I'm going to fix that. Next patch. I promise. llvm-svn: 229835
* Add an IR-to-IR test for dwarf EH preparation using optReid Kleckner2015-02-181-0/+8
| | | | | | | This tests the simple resume instruction elimination logic that we have before making some changes to it. llvm-svn: 229768
* Style and formatting fixes for r229715Andrew Kaylor2015-02-181-1/+0
| | | | llvm-svn: 229758
* dos2unix the WinEH file and testsReid Kleckner2015-02-181-391/+391
| | | | llvm-svn: 229735
* Remove unused member variables (-Wunused-private-field)David Blaikie2015-02-181-7/+3
| | | | llvm-svn: 229722
* Adding implementation to outline C++ catch handlers for native Windows 64 ↵Andrew Kaylor2015-02-181-102/+395
| | | | | | | | exception handling. Differential Revision: http://reviews.llvm.org/D7363 llvm-svn: 229715
* Fixes two issue in SimplifyDemandedBits of sext_in_reg:Michael Kuperstein2015-02-181-11/+18
| | | | | | | | | | | 1) We should not try to simplify if the sext has multiple uses 2) There is no need to simplify is the source value is already sign-extended. Patch by Gil Rapaport <gil.rapaport@intel.com> Differential Revision: http://reviews.llvm.org/D6949 llvm-svn: 229659
* NFC: Use range-based for loops and more consistent naming.Daniel Jasper2015-02-181-19/+15
| | | | | | | | | No functional changes intended. (I plan on doing some modifications to this function and would like to have as few unrelated changes as possible in the patch) llvm-svn: 229649
* Remove experimental options to control machine block placement.Daniel Jasper2015-02-181-35/+20
| | | | | | | This reverts r226034. Benchmarking with those flags has not revealed anything interesting. llvm-svn: 229648
* LiveRangeCalc: Rename some parameters from kill to use, NFC.Matthias Braun2015-02-183-36/+35
| | | | | | Those parameters did not necessarily describe kill points but just uses. llvm-svn: 229601
* Twines should be passed by const ref.Rafael Espindola2015-02-171-2/+2
| | | | llvm-svn: 229590
* Add r228939 back with a fix.Rafael Espindola2015-02-172-11/+11
| | | | | | | | | | | | | The problem in the original patch was not switching back to .text after printing an eh table. Original message: On ELF, put PIC jump tables in a non executable section. Fixes PR22558. llvm-svn: 229586
* AsmPrinter: Take range in DwarfExpression::AddExpression(), NFCDuncan P. N. Exon Smith2015-02-174-6/+11
| | | | | | | | | | Previously `DwarfExpression::AddExpression()` relied on default-constructing the end iterators for `DIExpression` -- once the operands are represented explicitly via `MDExpression` (instead of via the strange `StringRef` navigator in `DIHeaderIterator`) this won't work. Explicitly take an iterator for the end of the range. llvm-svn: 229572
* Add r228980 back.Rafael Espindola2015-02-171-14/+17
| | | | | | | | | | Add support for having multiple sections with the same name and comdat. Using this in combination with -ffunction-sections allows LLVM to output a .o file with mulitple sections named .text. This saves space by avoiding long unique names of the form .text.<C++ mangled name>. llvm-svn: 229541
* Make the ARM AsmPrinter independent of global subtargetEric Christopher2015-02-171-1/+1
| | | | | | | | | | | | | | | | | initialization. Initialize the subtarget once per function and migrate Emit{Start|End}OfAsmFile to either use attributes on the TargetMachine or get information from the subtarget we'd use for assembling. One bit (getISAEncoding) touched the general AsmPrinter and the debug output. Handle this one by passing the function for the subprogram down and updating all callers and users. The top-level-ness of the ARM attribute output for assembly is, by nature, contrary to how we'd want to do this for an LTO situation where we have multiple cpu architectures so this solution is good enough for now. llvm-svn: 229528
* 80-column fixups.Eric Christopher2015-02-172-8/+11
| | | | llvm-svn: 229527
* Canonicalize splats as build_vectors (PR22283)Sanjay Patel2015-02-172-28/+22
| | | | | | | | | | | | | | | | | | | | | | This is a follow-on patch to: http://reviews.llvm.org/D7093 That patch canonicalized constant splats as build_vectors, and this patch removes the constant check so we can canonicalize all splats as build_vectors. This fixes the 2nd test case in PR22283: http://llvm.org/bugs/show_bug.cgi?id=22283 The unfortunate code duplication between SelectionDAG and DAGCombiner is discussed in the earlier patch review. At least this patch is just removing code... This improves an existing x86 AVX test and changes codegen in an ARM test. Differential Revision: http://reviews.llvm.org/D7389 llvm-svn: 229511
* Prefer SmallVector::append/insert over push_back loops.Benjamin Kramer2015-02-177-36/+14
| | | | | | Same functionality, but hoists the vector growth out of the loop. llvm-svn: 229500
* AsmPrinter: Use DIExpression default constructor, NFCDuncan P. N. Exon Smith2015-02-171-1/+1
| | | | llvm-svn: 229464
* AsmPrinter: Stop creating DebugLocsDuncan P. N. Exon Smith2015-02-172-13/+3
| | | | | | | | | | | | | | | | While looking at a heap profile of a clang LTO bootstrap with -g, I noticed that 2.2% of memory in an `llvm-lto` of clang is from calling `DebugLoc::get()` in `collectVariableInfo()` (accounting for ~40% of memory used for `MDLocation`s). I suspect this was introduced by r226736, whose goal was to prevent uniquing of `DebugLoc`s (goal achieved, if so). There's no reason we need a `DebugLoc` here at all -- it was just being used for (in)convenient API -- so the fix is to pass the scope and inlined-at directly to `LexicalScopes::findInlinedScope()`. llvm-svn: 229459
* RegisterCoalescer: Don't rematerialize subregister definitions.Matthias Braun2015-02-161-0/+18
| | | | | | | | | | | We cannot simply rematerialize instructions which only defining a subregister, as the final value also depends on the previous instructions. This fixes test/CodeGen/R600/subreg-coalescer-bug.ll with subreg liveness enabled. llvm-svn: 229444
* RegisterCoalescer: Do not look for regclass of IMPLICIT_DEF.Matthias Braun2015-02-161-6/+7
| | | | | | | | | | | | IMPLICIT_DEF is a generic instruction and has no (fixed) output register class defined. The rematerialization code of the register coalescer should not scan the instruction description for a register class. This fixes a problem showing up in test/CodeGen/R600/subreg-coalescer-crash.ll with subregister liveness enabled. llvm-svn: 229443
* SelectionDAG: fold (fp_to_u/sint (s/uint_to_fp)) here tooMehdi Amini2015-02-161-2/+46
| | | | | | | Update SPARC tests to match. From: Fiona Glaser <fglaser@apple.com> llvm-svn: 229438
* RegisterCoalescer: Improve previous fix for wrong def after.Matthias Braun2015-02-161-3/+2
| | | | | | | | | | | The previous fix in r225503 was needlessly complicated. The problem goes away as well if the arguments to MergeValueNumberInto are supplied in the correct order. This was previously missed because the existing code already had the wrong order but an additional later Merge was hiding the bug for the main liverange VNI. llvm-svn: 229424
* MSVC 2013 supports std::forward_as_tuple, while MSVC 2012 did not; so we can ↵Aaron Ballman2015-02-161-10/+8
| | | | | | move to using the improved API. llvm-svn: 229414
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