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* Move the grabbing of the jump buffer into the caller function, eliminating ↵Bill Wendling2011-10-031-31/+33
| | | | | | the need for returning a std::pair. llvm-svn: 141026
* Whitespace.Eric Christopher2011-10-031-1/+1
| | | | llvm-svn: 141005
* Typo.Eric Christopher2011-10-031-1/+1
| | | | llvm-svn: 141004
* Moved type construction out of the loop and added an assert on the legality ↵Nadav Rotem2011-10-011-10/+10
| | | | | | of the type. Formatted lines to the 80 char limit. llvm-svn: 140952
* When inferring the pointer alignment, if the global doesn't have an initializerBill Wendling2011-09-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | and the alignment is 0 (i.e., it's defined globally in one file and declared in another file) it could get an alignment which is larger than the ABI allows for that type, resulting in aligned moves being used for unaligned loads. For instance, in file A.c: struct S s; In file B.c: struct { // something long }; extern S s; void foo() { struct S p = s; // ... } this copy is a 'memcpy' which is turned into a series of 'movaps' instructions on X86. But this is wrong, because 'struct S' has alignment of 4, not 16. llvm-svn: 140902
* Promote comment to doxycomment. Adjust whitespace. No functionality change.Nick Lewycky2011-09-301-4/+3
| | | | llvm-svn: 140899
* Move getCommonSubClass() into TRI.Jakob Stoklund Olesen2011-09-304-9/+10
| | | | | | It will soon need the context. llvm-svn: 140896
* Comment grammar fixes.Torok Edwin2011-09-301-5/+6
| | | | | | thanks to Duncan. llvm-svn: 140850
* Instead of crashing when MCAsmInfo is NULL, add an assert.Torok Edwin2011-09-301-0/+5
| | | | | | | This helps with porting code from 2.9 to 3.0 as TargetSelect.h changed location, and if you include the old one by accident you will trigger this assert. llvm-svn: 140848
* Clean up uses of switch instructions so they are not dependent on the ↵Eli Friedman2011-09-291-2/+2
| | | | | | operand ordering. Patch by Stepan Dyatkovskiy. llvm-svn: 140803
* Place this bracket according to the LLVM style.Duncan Sands2011-09-291-2/+1
| | | | llvm-svn: 140784
* Remove NumImplicitOps which is now unused.Jakob Stoklund Olesen2011-09-291-18/+12
| | | | llvm-svn: 140767
* Use the local we already set up.Eric Christopher2011-09-291-1/+1
| | | | llvm-svn: 140745
* Rewrite MachineInstr::addOperand() to avoid NumImplicitOps.Jakob Stoklund Olesen2011-09-291-81/+53
| | | | | | | | | | | | | | | | | | | | | | | The function needs to scan the implicit operands anyway, so no performance is won by caching the number of implicit operands added to an instruction. This also fixes a bug when adding operands after an implicit operand has been added manually. The NumImplicitOps count wasn't kept up to date. MachineInstr::addOperand() will now consistently place all explicit operands before all the implicit operands, regardless of the order they are added. It is possible to change an MI opcode and add additional explicit operands. They will be inserted before any existing implicit operands. The only exception is inline asm instructions where operands are never reordered. This is because of a hack that marks explicit clobber regs on inline asm as <implicit-def> to please the fast register allocator. This hack can go away when InstrEmitter and FastIsel can add exact <dead> flags to physreg defs. llvm-svn: 140744
* Have the SjLjEHPrepare pass do some more heavy lifting.Bill Wendling2011-09-281-34/+55
| | | | | | | | Upon further review, most of the EH code should remain written at the IR level. The part which breaks SSA form is the dispatch table, so that part will be moved to the back-end. llvm-svn: 140730
* A typeid of zero means a cleanup, not a catch. This case occursDuncan Sands2011-09-281-2/+4
| | | | | | when there is both a catch and a cleanup. Correct the comment. llvm-svn: 140686
* Strip off pointer casts when looking at the eh.sjlj.functioncontext's argument.Bill Wendling2011-09-281-1/+2
| | | | llvm-svn: 140678
* Bitcast the alloca to an i8* to match the intrinsic's signature.Bill Wendling2011-09-281-1/+4
| | | | llvm-svn: 140677
* Create and use an llvm.eh.sjlj.functioncontext intrinsic.Bill Wendling2011-09-282-0/+14
| | | | | | | | This intrinsic is used to pass the index of the function context to the back-end for further processing. The back-end is in charge of filling in the rest of the entries. llvm-svn: 140676
* In the new EH model, setup the function context and the call site info.Bill Wendling2011-09-281-1/+181
| | | | | | | | | | | | The DWARF exception pass uses the call site information, which is set up here. A pre-RA pass is too late for it to use this information. So create and setup the function context here, and then insert the call site values here (and map the call sites for the DWARF EH pass). This is simpler than the original pass, and doesn't make the CFG lose its SSA-ness. It's a win-win-win-win-lose-win-win situation. llvm-svn: 140675
* Don't conditionalize execution of the SjLj EH prepare pass.Bill Wendling2011-09-281-5/+1
| | | | | | | We may need an SjLj EH preparation pass for some call site information, at least in the short term. llvm-svn: 140674
* Rename class and clean up source.Jakob Stoklund Olesen2011-09-281-25/+28
| | | | | | No functional change intended. llvm-svn: 140664
* Rename SSEDomainFix -> lib/CodeGen/ExecutionDepsFix.Jakob Stoklund Olesen2011-09-282-0/+521
| | | | | | I'll clean up the source in the next commit. llvm-svn: 140663
* This is the start of the new SjLj EH preparation pass, which will replace theBill Wendling2011-09-271-1/+5
| | | | | | | | | | | | | | | | | | | current IR-level pass. The old SjLj EH pass has some problems, especially with the new EH model. Most significantly, it violates some of the new restrictions the new model has. For instance, the 'dispatch' table wants to jump to the landing pad, but we cannot allow that because only an invoke's unwind edge can jump to a landing pad. This requires us to mangle the code something awful. In addition, we need to keep the now dead landingpad instructions around instead of CSE'ing them because the DWARF emitter uses that information (they are dead because no control flow edge will execute them - the control flow edge from an invoke's unwind is superceded by the edge coming from the dispatch). Basically, this pass belongs not at the IR level where SSA is king, but at the code-gen level, where we have more flexibility. llvm-svn: 140646
* Remove an invalid assert that is really just asserting when the scheduler emitsCameron Zwarich2011-09-271-1/+0
| | | | | | a suboptimal schedule. llvm-svn: 140643
* Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId().Jim Grosbach2011-09-271-2/+2
| | | | | | Naming conventions consistency. No functional change. llvm-svn: 140636
* Cleanup PromoteIntOp_EXTRACT_VECTOR_ELT and PromoteIntRes_SETCC.Nadav Rotem2011-09-272-10/+12
| | | | | | Add a new method: getAnyExtOrTrunc and use it to replace the manual check. llvm-svn: 140603
* Revert r140463; The patch assumes that <4 x i1> is saved to memory as 4 x i8,Nadav Rotem2011-09-271-10/+1
| | | | | | while the decision is to bit-pack small values. llvm-svn: 140601
* Fix emission of debug data for global variables. getContext() on ↵James Molloy2011-09-261-2/+2
| | | | | | DIGlobalVariables is not valid any more. llvm-svn: 140539
* Add target hook for pseudo instruction expansion.Jakob Stoklund Olesen2011-09-251-7/+16
| | | | | | | | | | | | Many targets use pseudo instructions to help register allocation. Like the COPY instruction, these pseudos can be expanded after register allocation. The early expansion can make life easier for PEI and the post-ra scheduler. This patch adds a hook that is called for all remaining pseudo instructions from the ExpandPostRAPseudos pass. llvm-svn: 140472
* [vector-select] Address one of the issues in pr10902. EXTRACT_VECTOR_ELEMENTNadav Rotem2011-09-251-2/+7
| | | | | | | | | SDNodes may return values which are wider than the incoming element types. In this patch we fix the integer promotion of these nodes. Fixes spill-q.ll when running -promote-elements. llvm-svn: 140471
* Clean up code after renaming LowerSubregs -> ExpandPostRAPseudos.Jakob Stoklund Olesen2011-09-252-45/+42
| | | | | | No functional change intended. llvm-svn: 140470
* Rename LowerSubregs to ExpandPostRAPseudos.Jakob Stoklund Olesen2011-09-252-1/+1
| | | | | | | | | | | | | | I'll fix the file contents in the next commit. This pass is currently expanding the COPY and SUBREG_TO_REG pseudos. I am going to add a hook so targets can expand more pseudo-instructions after register allocation. Many targets have pseudo-instructions that assist the register allocator. They can be expanded after register allocation, before PEI and PostRA scheduling. llvm-svn: 140469
* Implement Duncan's suggestion to use the result of getSetCCResultType if it ↵Nadav Rotem2011-09-241-4/+9
| | | | | | | | | | is legal (this is always the case for scalars), otherwise use the promoted result type. Fix test/CodeGen/X86/vsplit-and.ll when promote-elements is enabled. llvm-svn: 140464
* [Vector-Select] Address one of the problems in 10902.Nadav Rotem2011-09-241-1/+10
| | | | | | | | | | When generating the trunc-store of i1's, we need to use the vector type and not the scalar type. This patch fixes the assertion in CodeGen/Generic/bool-vector.ll when running with -promote-elements. llvm-svn: 140463
* Verify that terminators follow non-terminators.Jakob Stoklund Olesen2011-09-231-0/+13
| | | | | | This exposes a -segmented-stacks bug. llvm-svn: 140429
* PR10998: It is not legal to sink an instruction past the terminator of a ↵Eli Friedman2011-09-231-1/+9
| | | | | | block; make sure we don't do that. llvm-svn: 140428
* Tweak the handling of MERGE_VALUES nodes: remove the need forDuncan Sands2011-09-236-51/+43
| | | | | | | | | DecomposeMERGE_VALUES to "know" that results are legalized in a particular order, by passing it the number of the result being legalized (the type legalization core provides this, it just needs to be passed on). llvm-svn: 140373
* Vector-Select: Address one of the problems in pr10902. Add handling for theNadav Rotem2011-09-232-0/+43
| | | | | | | | | | integer-promotion of CONCAT_VECTORS. Test: test/CodeGen/X86/widen_shuffle-1.ll This patch fixes the above tests (when running in with -promote-elements). llvm-svn: 140372
* Fix SimplifySelectCC to add newly created nodes to the DAGCombinerDan Gohman2011-09-221-0/+3
| | | | | | worklist, as it may be possible to perform further optimization on them. llvm-svn: 140349
* Constrain register classes instead of emitting copies.Jakob Stoklund Olesen2011-09-221-3/+5
| | | | | | | | | | | Sometimes register class constraints are trivial, like GR32->GR32_NOSP, or GPR->rGPR. Teach InstrEmitter to simply constrain the virtual register instead of emitting a copy in these cases. Normally, these copies are handled by the coalescer. This saves some coalescer work. llvm-svn: 140340
* Add a MinNumRegs argument to MRI::constrainRegClass().Jakob Stoklund Olesen2011-09-221-4/+6
| | | | | | | | | | | The function will refuse to use a register class with fewer registers than MinNumRegs. This can be used by clients to avoid accidentally increase register pressure too much. The default value of MinNumRegs=0 doesn't affect how constrainRegClass() works. llvm-svn: 140339
* Use the C personality function instead of the C++ personality function.Bill Wendling2011-09-221-3/+1
| | | | llvm-svn: 140318
* Do not unnecessarily use AT_specification DIE because it does not add any value.Devang Patel2011-09-211-1/+1
| | | | | | Few weeks ago, llvm completely inverted the debug info graph. Earlier each debug info node used to keep track of its compile unit, now compile unit keeps track of important nodes. One impact of this change is that the global variable's do not have any context, which should be checked before deciding to use AT_specification DIE. llvm-svn: 140282
* Attempt to update the shadow stack GC pass to the new EH model.Bill Wendling2011-09-211-5/+17
| | | | | | | This inserts a cleanup landingpad instruction and a resume to mimic the old unwind instruction. llvm-svn: 140277
* Tidy up. Whitepsace.Jim Grosbach2011-09-211-3/+3
| | | | llvm-svn: 140275
* [VECTOR-SELECT] Address one of the bugs in pr10902.Nadav Rotem2011-09-211-0/+2
| | | | | | | Vector SetCC result types need to be type-legalized. This code worked before because scalar result types are known to be legal. llvm-svn: 140249
* Lower ARM adds/subs to add/sub after adding optional CPSR operand.Andrew Trick2011-09-213-6/+8
| | | | | | | | | | | | | This is still a hack until we can teach tblgen to generate the optional CPSR operand rather than an implicit CPSR def. But the strangeness is now limited to the selection DAG. ADD/SUB MI's no longer have implicit CPSR defs, nor do we allow flag setting variants of these opcodes in machine code. There are several corner cases to consider, and getting one wrong would previously lead to nasty miscompilation. It's not the first time I've debugged one, so this time I added enough verification to ensure it won't happen again. llvm-svn: 140228
* Add a DAGCombine for subvector extracts to remove useless chains ofBruno Cardoso Lopes2011-09-201-0/+32
| | | | | | | subvector inserts and extracts. Initial patch by Rackover, Zvi with some tweak done by me. llvm-svn: 140204
* Restore hasPostISelHook tblgen flag.Andrew Trick2011-09-202-2/+8
| | | | | | | | | | No functionality change. The hook makes it explicit which patterns require "special" handling. i.e. it self-documents tblgen deficiencies. I plan to add verification in ExpandISelPseudos and Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's too fragile. llvm-svn: 140160
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