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* Debug Info: Support fragmented variables in the MMI side tableAdrian Prantl2017-07-251-1/+6
| | | | | | <rdar://problem/17816343> llvm-svn: 309034
* [DAG] Move DAGCombiner::GetDemandedBits to SelectionDAGSimon Pilgrim2017-07-252-62/+58
| | | | | | | | This patch moves the DAGCombiner::GetDemandedBits function to SelectionDAG::GetDemandedBits as a first step towards making it easier for targets to get to the source of any demanded bits without the limitations of SimplifyDemandedBits. Differential Revision: https://reviews.llvm.org/D35841 llvm-svn: 308983
* Fix endianness bug in DAGCombiner::visitTRUNCATE and visitEXTRACT_VECTOR_ELTFrancois Pichet2017-07-251-4/+7
| | | | | | | | | | | | | | | | Summary: Do not assume little endian architecture in DAGCombiner::visitTRUNCATE and DAGCombiner::visitEXTRACT_VECTOR_ELT. PR33682 Reviewers: hfinkel, sdardis, RKSimon Reviewed By: sdardis, RKSimon Subscribers: uabelho, RKSimon, sdardis, llvm-commits Differential Revision: https://reviews.llvm.org/D34990 llvm-svn: 308960
* RA: Replace asserts related to empty live intervalsMatt Arsenault2017-07-242-4/+9
| | | | | | | | | These don't exactly assert the same thing anymore, and allow empty live intervals with non-empty uses. Removed in r308808 and r308813. llvm-svn: 308906
* [CodeGenPrepare] Cut off FindAllMemoryUses if there are too many uses.Benjamin Kramer2017-07-241-4/+13
| | | | | | | | | | | | | | | | | | | This avoids excessive compile time. The case I'm looking at is Function.cpp from an old version of LLVM that still had the giant memcmp string matcher in it. Before r308322 this compiled in about 2 minutes, after it, clang takes infinite* time to compile it. With this patch we're at 5 min, which is still bad but this is a pathological case. The cut off at 20 uses was chosen by looking at other cut-offs in LLVM for user scanning. It's probably too high, but does the job and is very unlikely to regress anything. Fixes PR33900. * I'm impatient and aborted after 15 minutes, on the bug report it was killed after 2h. llvm-svn: 308891
* [codeview] Emit 'D' as the cv source language for D codeReid Kleckner2017-07-241-0/+2
| | | | | | | | | This matches DMD: https://github.com/dlang/dmd/blob/522263965cf3a27ed16b31f3c3562db86cdeabec/src/ddmd/backend/cv8.c#L199 Fixes PR33899. llvm-svn: 308890
* Format some case labels and shrink an anonymous namespace NFCReid Kleckner2017-07-241-15/+12
| | | | llvm-svn: 308889
* [CodeGen][X86] Fuchsia supports sincos* libcalls and sin+cos->sincos ↵Petr Hosek2017-07-231-1/+1
| | | | | | | | | | optimization Patch by Roland McGrath Differential Revision: https://reviews.llvm.org/D35748 llvm-svn: 308854
* [DAG] Fix typo preventing some stores merges to truncated stores.Nirav Dave2017-07-231-4/+4
| | | | | | | | | | | | | | | Check the actual memory type stored and not the extended value size when considering if truncated store merge is worthwhile. Reviewers: efriedma, RKSimon, spatel, jyknight Reviewed By: efriedma Subscribers: llvm-commits, nhaehnle Differential Revision: https://reviews.llvm.org/D35623 llvm-svn: 308833
* RA: Remove another assert on empty intervalsMatt Arsenault2017-07-221-2/+2
| | | | | | | | | This case is similar to the one fixed in r308808, except when rematerializing. Fixes bug 33884. llvm-svn: 308813
* RA: Remove assert on empty live intervalsMatt Arsenault2017-07-211-1/+0
| | | | | | | | | This is possible if there is an undef use when splitting the vreg during spilling. Fixes bug 33620. llvm-svn: 308808
* [DAGCombiner] Update comment. NFCXin Tong2017-07-211-1/+1
| | | | llvm-svn: 308772
* [SystemZ, LoopStrengthReduce]Jonas Paulsson2017-07-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes LSR generate better code for SystemZ in the cases of memory intrinsics, Load->Store pairs or comparison of immediate with memory. In order to achieve this, the following common code changes were made: * New TTI hook: LSRWithInstrQueries(), which defaults to false. Controls if LSR should do instruction-based addressing evaluations by calling isLegalAddressingMode() with the Instruction pointers. * In LoopStrengthReduce: handle address operands of memset, memmove and memcpy as address uses, and call isFoldableMemAccessOffset() for any LSRUse::Address, not just loads or stores. SystemZ changes: * isLSRCostLess() implemented with Insns first, and without ImmCost. * New function supportedAddressingMode() that is a helper for TTI methods looking at Instructions passed via pointers. Review: Ulrich Weigand, Quentin Colombet https://reviews.llvm.org/D35262 https://reviews.llvm.org/D35049 llvm-svn: 308729
* Commit access testPhilipp Schaad2017-07-211-1/+1
| | | | llvm-svn: 308712
* Debug Info: Don't strip clang module skeleton CUs.Adrian Prantl2017-07-211-1/+2
| | | | | | | | This corrects a (hopefully :-) accidental side-effect of r304020. rdar://problem/33442618 llvm-svn: 308708
* GlobalISel: stop localizer putting constants before EH_LABELsTim Northover2017-07-201-1/+2
| | | | | | | | If the localizer pass puts one of its constants before the label that tells the unwinder "jump here to handle your exception" then control-flow will skip it, leaving uninitialized registers at runtime. That's bad. llvm-svn: 308687
* Add an ID field to StackObjectsMatt Arsenault2017-07-205-5/+22
| | | | | | | | | | | | | | | | | | | | | On AMDGPU SGPR spills are really spilled to another register. The spiller creates the spills to new frame index objects, which is used as a placeholder. This will eventually be replaced with a reference to a position in a VGPR to write to and the frame index deleted. It is most likely not a real stack location that can be shared with another stack object. This is a problem when StackSlotColoring decides it should combine a frame index used for a normal VGPR spill with a real stack location and a frame index used for an SGPR. Add an ID field so that StackSlotColoring has a way of knowing the different frame index types are incompatible. llvm-svn: 308673
* [PEI] Fix refactoring from r308664Francis Visoiu Mistrih2017-07-201-1/+1
| | | | llvm-svn: 308666
* [COFF, ARM64, CodeView] Add support to emit CodeView debug info for ARM64 COFFMandeep Singh Grang2017-07-201-0/+2
| | | | | | | | | | | | Reviewers: compnerd, ruiu, rnk, zturner Reviewed By: rnk Subscribers: majnemer, aemerson, aprantl, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D35518 llvm-svn: 308665
* [PEI] Separate saving and restoring CSRs into different functions. NFCFrancis Visoiu Mistrih2017-07-201-66/+51
| | | | | | | | | | | Split insertCSRSpillsAndRestores into insertCSRSaves + insertCSRRestores. This is mostly useful for future shrink-wrapping improvements where we want to save / restore a specific part of the CSRs in a specific block. Differential Revision: https://reviews.llvm.org/D35644 llvm-svn: 308664
* Implement LaneBitmask::getNumLanes and LaneBitmask::getHighestLaneKrzysztof Parzyszek2017-07-201-3/+3
| | | | | | | This should eliminate most uses of countPopulation and Log2_32 on the lane mask values. llvm-svn: 308658
* Use LaneBitmask::getLane in a few more placesKrzysztof Parzyszek2017-07-201-2/+2
| | | | llvm-svn: 308655
* [DAG] Commit missed nit cleanup from r308617. NFC.Nirav Dave2017-07-201-1/+1
| | | | llvm-svn: 308645
* [DAG] Handle missing transform in fold of value extension case.Nirav Dave2017-07-201-0/+14
| | | | | | | | | | | | | | | Summary: When pushing an extension of a constant bitwise operator on a load into the load, change other uses of the load value if they exist to prevent the old load from persisting. Reviewers: spatel, RKSimon, efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35030 llvm-svn: 308618
* [DAG] Optimize away degenerate INSERT_VECTOR_ELT nodes.Nirav Dave2017-07-201-0/+6
| | | | | | | | | | | | | | | | | Summary: Add missing vector write of vector read reduction, i.e.: (insert_vector_elt x (extract_vector_elt x idx) idx) to x Reviewers: spatel, RKSimon, efriedma Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35563 llvm-svn: 308617
* [DAGCombiner] Match ISD::SRL non-uniform constant vectors patterns using ↵Simon Pilgrim2017-07-201-13/+26
| | | | | | | | predicates. Use predicate matchers introduced in D35492 to match more ISD::SRL constant folds llvm-svn: 308602
* Remove trailing whitespace. NFCI.Simon Pilgrim2017-07-201-1/+1
| | | | llvm-svn: 308601
* [DAGCombiner] Match ISD::SRA non-uniform constant vectors patterns using ↵Simon Pilgrim2017-07-201-13/+28
| | | | | | | | predicates. Use predicate matchers introduced in D35492 to match more ISD::SRA constant folds llvm-svn: 308600
* [DAGCombiner] Match non-uniform constant vectors using predicates.Simon Pilgrim2017-07-201-28/+81
| | | | | | | | | | | | Most combines currently recognise scalar and splat-vector constants, but not non-uniform vector constants. This patch introduces a matching mechanism that uses predicates to check against BUILD_VECTOR of ConstantSDNode, as well as scalar ConstantSDNode cases. I've changed a couple of predicates to demonstrate - the combine-shl changes add currently unsupported cases, while the MatchRotate replaces an existing mechanism. Differential Revision: https://reviews.llvm.org/D35492 llvm-svn: 308598
* Revert "[PEI] Simplify handling of targets with no phys regs. NFC"Francis Visoiu Mistrih2017-07-201-8/+23
| | | | | | | | This reverts commit ce30ab6e5598f3c24f59ad016dc9526bc9a1d450. sanitizer-ppc64le-linux seems to segfault when testing the sanitizers. llvm-svn: 308581
* Revert "[PEI] Separate saving and restoring CSRs into different functions. NFC"Francis Visoiu Mistrih2017-07-201-51/+66
| | | | | | | | This reverts commit 540f6a26ae932469804a379ce9a8cbe715d59c23. sanitizer-ppc64le-linux seems to segfault when testing the sanitizers. llvm-svn: 308580
* [PEI] Separate saving and restoring CSRs into different functions. NFCFrancis Visoiu Mistrih2017-07-201-66/+51
| | | | | | | | | | | Split insertCSRSpillsAndRestores into insertCSRSaves + insertCSRRestores. This is mostly useful for future shrink-wrapping improvements where we want to save / restore a specific part of the CSRs in a specific block. Differential Revision: https://reviews.llvm.org/D35644 llvm-svn: 308573
* Replace -print-whole-regmask with a threshold.Matt Arsenault2017-07-201-5/+8
| | | | | | | | The previous flag/default of printing everything is not helpful when there are thousands of registers in the mask. llvm-svn: 308572
* Revert "[PEI] Separate saving and restoring CSRs into different functions. NFC"Francis Visoiu Mistrih2017-07-201-51/+66
| | | | | | This reverts commit a84d1fa6847e70ebf63594d41a00b473c941bd72. llvm-svn: 308562
* [AsmPrinter] Constify needsCFIMoves. NFCFrancis Visoiu Mistrih2017-07-191-1/+1
| | | | llvm-svn: 308557
* [PEI] Add basic opt-remarks supportFrancis Visoiu Mistrih2017-07-191-0/+13
| | | | | | | | | | Add optimization remarks support to the PrologueEpilogueInserter. For now, emit the stack size as an analysis remark, but more additions wrt shrink-wrapping may be added. https://reviews.llvm.org/D35645 llvm-svn: 308556
* [PEI] Simplify handling of targets with no phys regs. NFCFrancis Visoiu Mistrih2017-07-191-23/+8
| | | | | | | | | Make doSpillCalleeSavedRegs a member function, instead of passing most of the members of PEI as arguments. Differential Revision: https://reviews.llvm.org/D35642 llvm-svn: 308555
* [PEI] Separate saving and restoring CSRs into different functions. NFCFrancis Visoiu Mistrih2017-07-191-66/+51
| | | | | | | | | | | Split insertCSRSpillsAndRestores into insertCSRSaves + insertCSRRestores. This is mostly useful for future shrink-wrapping improvements where we want to save / restore a specific part of the CSRs in a specific block. Differential Revision: https://reviews.llvm.org/D35644 llvm-svn: 308554
* Move Runtime libcall definitions to a .def fileDerek Schuff2017-07-191-438/+8
| | | | | | | | | This will allow eliminating the duplication of the names, and allow adding extra information such as signatures in a future commit. Differential Revision: https://reviews.llvm.org/D35522 llvm-svn: 308531
* Fixing an issue with the initialization of LexicalScopes objects when mixing ↵Wolfgang Pieb2017-07-192-2/+10
| | | | | | | | | | | | debug and non-debug units. Patch by Andrea DiBiagio. Differential Revision: https://reviews.llvm.org/D35637 llvm-svn: 308513
* {DAGCombine] Convert (Val & Mask) == Mask to Mask.isSubsetof(Val). NFCI.Simon Pilgrim2017-07-191-1/+1
| | | | llvm-svn: 308460
* [CGP] Allow cycles during Phi traversal in OptimizaMemoryInstSerguei Katkov2017-07-191-5/+11
| | | | | | | | | | | | | | Allowing cycles in Phi traversal increases the scope of optimize memory instruction in case we are in loop. The added test shows an example of enabling optimization inside a loop. Reviewers: loladiro, spatel, efriedma Reviewed By: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35294 llvm-svn: 308419
* Debug Info: Add a file: field to DIImportedEntity.Adrian Prantl2017-07-191-2/+3
| | | | | | | | | | | | | | | | | | | | | | | DIImportedEntity has a line number, but not a file field. To determine the decl_line/decl_file we combine the line number from the DIImportedEntity with the file from the DIImportedEntity's scope. This does not work correctly when the parent scope is a DINamespace or a DIModule, both of which do not have a source file. This patch adds a file field to DIImportedEntity to unambiguously identify the source location of the using/import declaration. Most testcase updates are mechanical, the interesting one is the removal of the FIXME in test/DebugInfo/Generic/namespace.ll. This fixes PR33822. See https://bugs.llvm.org/show_bug.cgi?id=33822 for more context. <rdar://problem/33357889> https://bugs.llvm.org/show_bug.cgi?id=33822 Differential Revision: https://reviews.llvm.org/D35583 llvm-svn: 308398
* [DAG] Improve Aliasing of operations to static allocaNirav Dave2017-07-181-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Re-recommiting after landing DAG extension-crash fix. Recommiting after adding check to avoid miscomputing alias information on addresses of the same base but different subindices. Memory accesses offset from frame indices may alias, e.g., we may merge write from function arguments passed on the stack when they are contiguous. As a result, when checking aliasing, we consider the underlying frame index's offset from the stack pointer. Static allocs are realized as stack objects in SelectionDAG, but its offset is not set until post-DAG causing DAGCombiner's alias check to consider access to static allocas to frequently alias. Modify isAlias to consider access between static allocas and access from other frame objects to be considered aliasing. Many test changes are included here. Most are fixes for tests which indirectly relied on our aliasing ability and needed to be modified to preserve their original intent. The remaining tests have minor improvements due to relaxed ordering. The exception is CodeGen/X86/2011-10-19-widen_vselect.ll which has a minor degradation dispite though the pre-legalized DAG is improved. Reviewers: rnk, mkuper, jonpa, hfinkel, uweigand Reviewed By: rnk Subscribers: sdardis, nemanjai, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33345 llvm-svn: 308350
* [DAG] Reverse node replacement in extension operation. NFCI.Nirav Dave2017-07-181-12/+20
| | | | | | | | Reorder replacements to be user first in preparation for multi-level folding to premptively avoid inadvertantly deleting later nodes from sharing found from replacement. llvm-svn: 308348
* [DAG] Avoid deleting nodes before combining them.Nirav Dave2017-07-181-7/+26
| | | | | | | | | | | | | | | | | | When replacing a node and it's operand, replacing the operand node may cause the deletion of the original node leading to an assertion failure. Case around these replacements to avoid this without relying on inspecting the DELETED_NODE opcode in various extend dagcombiner cases. Fixes PR32515. Reviewers: dbabokin, RKSimon, davide, chandlerc Subscribers: chandlerc, llvm-commits Differential Revision: https://reviews.llvm.org/D34095 llvm-svn: 308330
* [DAG] Allow base element type of store merge type to also be a vector.Nirav Dave2017-07-181-1/+6
| | | | | | Correctly calculate merged vector size if MemVT is already a vector. llvm-svn: 308312
* [DAGCombine] Fix issue with out of bound constant rotation (PR33828)Simon Pilgrim2017-07-181-1/+10
| | | | | | Take the modulo of rotations by a constant greater than or equal to the bit-width llvm-svn: 308302
* GlobalISel: Support G_(S|U)REM widening in LegalizerHelperDiana Picus2017-07-181-0/+3
| | | | | | | | Treat widening G_SREM and G_UREM the same as G_SDIV and G_UDIV. This is going to be used in the ARM backend (and that's when the test will come too). llvm-svn: 308278
* Revert r308025 due to uncovering a crash in SelectionDAG. This is filedChandler Carruth2017-07-181-16/+6
| | | | | | | | | with a minimal test case in http://llvm.org/PR33833. Original commit message: Improve Aliasing of operations to static alloca llvm-svn: 308271
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