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* [ARM, AArch64] Match additional patterns to ldN instructionsMatthew Simpson2016-05-191-5/+107
| | | | | | | | | | | | | | When matching an interleaved load to an ldN pattern, the interleaved access pass checks that all users of the load are shuffles. If the load is used by an instruction other than a shuffle, the pass gives up and an ldN is not generated. This patch considers users of the load that are extractelement instructions. It attempts to modify the extracts to use one of the available shuffles rather than the load. After the transformation, the load is only used by shuffles and will then be matched with an ldN pattern. Differential Revision: http://reviews.llvm.org/D20250 llvm-svn: 270142
* Modify emitTypeInformation to use MemoryTypeTableBuilderAdrian McCarthy2016-05-192-42/+19
| | | | | | | | A baby step toward translating DIType records to CodeView. This does not (yet) combine the record length with the record data. I'm going back and forth trying to determine if that's a good idea. llvm-svn: 270106
* [ARM, AArch64] Properly initialize InterleavedAccessPassMatthew Simpson2016-05-192-4/+1
| | | | | | | InterleavedAccessPass is an IR-level pass, so this change will enable testing it with opt. This is part of D20250. llvm-svn: 270101
* CodeGen: Move check of EnablePostRAScheduler to avoid disabling ↵Mitch Bodart2016-05-191-11/+12
| | | | | | | | | | | | antidependency breaker Previously, specifying -post-RA-scheduler=true had the side effect of disabling the antidependency breaker, yielding different behavior than if the post-RA-scheduler was enabled via the scheduling model. Differential Revision: http://reviews.llvm.org/D20186 llvm-svn: 270077
* [SelectionDAG] rename/move isKnownToBeAPowerOfTwo() from TargetLowering (NFC)Sanjay Patel2016-05-192-32/+30
| | | | | | | | | There are at least 2 places (DAGCombiner, X86ISelLowering) where this could be used instead of ad-hoc and watered down code that is trying to match a power-of-2 pattern. Differential Revision: http://reviews.llvm.org/D20439 llvm-svn: 270073
* CodeGen: Make the global-merge pass independently testable, and add a test.Peter Collingbourne2016-05-191-7/+20
| | | | llvm-svn: 270023
* reduce indentation; NFCISanjay Patel2016-05-191-9/+7
| | | | llvm-svn: 270007
* [MBP] Remove a redundant skipFunction(). NFC.Haicheng Wu2016-05-181-3/+0
| | | | | | | | skipFunction() is called twice. Differential Revision: http://reviews.llvm.org/D20377 llvm-svn: 269994
* When looking for a spill slot in reg scavenger, find one that matches RCKrzysztof Parzyszek2016-05-181-7/+38
| | | | | | | | | | | | When looking for an available spill slot, the register scavenger would stop after finding the first one with no register assigned to it. That slot may have size and alignment that do not meet the requirements of the register that is to be spilled. Instead, find an available slot that is the closest in size and alignment to one that is needed to spill a register from RC. Differential Revision: http://reviews.llvm.org/D20295 llvm-svn: 269969
* Re-commit r269828 "X86: Avoid using _chkstk when lowering WIN_ALLOCA ↵Hans Wennborg2016-05-181-0/+5
| | | | | | | | | | | | instructions" with an additional fix to make RegAllocFast ignore undef physreg uses. It would previously get confused about the "push %eax" instruction's use of eax. That method for adjusting the stack pointer is used in X86FrameLowering::emitSPUpdate as well, but since that runs after register-allocation, we didn't run into the RegAllocFast issue before. llvm-svn: 269949
* [codeview] Some cleanup of Symbol Records.Zachary Turner2016-05-171-9/+9
| | | | | | | | | | | | | | * Reworks the CVSymbolTypes.def to work similarly to TypeRecords.def. * Moves some enums from SymbolRecords.h to CodeView.h to maintain consistency with how we do type records. * Generalize a few simple things like the record prefix * Define the leaf enum and the kind enum similar to how we do with tyep records. Differential Revision: http://reviews.llvm.org/D20342 Reviewed By: amccarth, rnk llvm-svn: 269867
* [DwarfDebug] Make tuning predicates private, should be used only in ctor.Paul Robinson2016-05-171-9/+10
| | | | llvm-svn: 269859
* Debug Info: Introduce a DwarfDebug::UseDWARF2Bitfields flagAdrian Prantl2016-05-173-6/+13
| | | | | | | | | instead of having DwarfUnit query the debugger tuning options. Follow-up commmit to r269827. Thanks to Paul Robinson for pointing this out! llvm-svn: 269840
* Debug Info: Don't emit bitfields in the DWARF4 format when tuning for GDB.Adrian Prantl2016-05-171-6/+11
| | | | | | | As discovered in PR27758, GDB does not fully support the DWARF 4 format. This patch ensures we always emit bitfields in the DWARF 2 when tuning for GDB. llvm-svn: 269827
* Fix an assert in SelectionDAGBuilder when processing inline asmRenato Golin2016-05-172-25/+30
| | | | | | | | | | | | | | When processing inline asm that contains errors, make sure we can recover gracefully by creating an UNDEF SDValue for the inline asm statement before returning from SelectionDAGBuilder::visitInlineAsm. This is necessary for consumers that don't exit on the first error that is emitted (e.g. clang) and that would assert later on. Fixes PR24071. Patch by Diana Picus. llvm-svn: 269811
* Simplify handling of hidden stub.Rafael Espindola2016-05-171-3/+1
| | | | | | | | | Since r207518 they are printed exactly like non-hidden stubs on x86 and since r207517 on ARM. This means we can use a single set for all stubs in those platforms. llvm-svn: 269776
* Factor PrologEpilogInserter around spilling, frame finalization, and scavengingDerek Schuff2016-05-172-80/+141
| | | | | | | | | | | | | | | PrologEpilogInserter has these 3 phases, which are related, but not all of them are needed by all targets. This patch reorganizes PEI's varous functions around those phases for more clear separation. It also introduces a new TargetMachine hook, usesPhysRegsForPEI, which is true for non-virtual targets. When it is true, all the phases operate as before, and PEI requires the AllVRegsAllocated property on MachineFunctions. Otherwise, CSR spilling and scavenging are skipped and only prolog/epilog insertion/frame finalization is done. Differential Revision: http://reviews.llvm.org/D18366 llvm-svn: 269750
* Debug Info: Don't emit a DW_AT_data_member_location for DWARF bitfields.Adrian Prantl2016-05-171-3/+3
| | | | | | | | | The DWARF spec states that a member entry may have either a DW_AT_data_member_location or a DW_AT_data_bit_offset, but not both. This fixes a bug found in PR 27758. llvm-svn: 269731
* Remove .hot and .unlikely prefixes from function section names.Easwaran Raman2016-05-161-16/+2
| | | | | | This code currently relies on static methods in ProfileSummary to determine whether a function is hot or unlikley. I am refactoring the ProfileSummary code and these methods will be removed. As discussed offline, the right way to re-introduce this is to add a pass to annotate functions with unlikely/hot hints and use the hints to determine the prefix here. llvm-svn: 269726
* Debug info: Don't emit a DW_AT_byte_size when emitting a DWARF4 bit field.Adrian Prantl2016-05-161-1/+2
| | | | | | | | | | The DWARF spec clearly states that a bit field member should have either a DW_AT_byte_size or a DW_AT_bit_size, but not both. Also the DW_AT_byte_size is redundant with the size of the type of the member. This fixes a bug found in PR 27758. llvm-svn: 269714
* Fail early on unknown appending linkage variables.Rafael Espindola2016-05-161-6/+3
| | | | | | | | | | | | | In practice only a few well known appending linkage variables work. Currently if codegen sees an unknown appending linkage variable it will just print it as a regular global. That is wrong as the symbol in the produced object file has different semantics as the one provided by the appending linkage. This just errors early instead of producing a broken .o. llvm-svn: 269706
* SelectionDAG: Select min/max when both are usedMatt Arsenault2016-05-161-1/+9
| | | | | | | | | | | Allow two users of the condition if the other user is also a min/max select. i.e. %c = icmp slt i32 %x, %y %min = select i1 %c, i32 %x, i32 %y %max = select i1 %c, i32 %y, i32 %x llvm-svn: 269699
* Remove extra whitespace. NFC.Chad Rosier2016-05-161-1/+1
| | | | llvm-svn: 269685
* [codeview] Align class and print names of typesReid Kleckner2016-05-131-1/+1
| | | | | | | | | | | | Summary: This way we can get rid of one of the fields in the .def file. Reviewers: llvm-commits Subscribers: zturner Differential Revision: http://reviews.llvm.org/D20251 llvm-svn: 269461
* Rename getLargestLegalIntTypeSize to getLargestLegalIntTypeSizeInBits(). NFC.Jun Bum Lim2016-05-132-2/+2
| | | | | | | | | | | | Summary: Rename DataLayout::getLargestLegalIntTypeSize to DataLayout::getLargestLegalIntTypeSizeInBits() to prevent similar mistakes fixed in r269433. Reviewers: joker.eph, mcrosier Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D20248 llvm-svn: 269456
* Revert "LiveIntervalAnalysis: Rework constructMainRangeFromSubranges()"Tom Stellard2016-05-124-48/+246
| | | | | | | | This reverts commit r269016 and also the follow-up commit r269020. This patch caused PR27705. llvm-svn: 269344
* Fix option description /NFCXinliang David Li2016-05-121-2/+2
| | | | llvm-svn: 269307
* [SelectionDAG] Attempt to split BITREVERSE vector legalization into BSWAP ↵Simon Pilgrim2016-05-121-5/+32
| | | | | | | | | | | | | | and BITREVERSE stages For BITREVERSE, bit shifting/masking every bit in a vector element is a very lengthy procedure. If the input vector type is a whole multiple of bytes wide then we can split this into a BSWAP shuffle stage (to reverse at the byte level) and then a BITREVERSE stage applied to each byte. Most vector capable targets can efficiently BSWAP using shuffles resulting in a considerable reduction in instructions. With this patch targets would only need to implement a target specific vXi8 BITREVERSE implementation to efficiently reverse most legal vector types. Differential Revision: http://reviews.llvm.org/D19978 llvm-svn: 269290
* [Layout] Add a new option (NFC)Xinliang David Li2016-05-121-1/+7
| | | | | | | | | | Currently cost based loop rotation algo can only be turned on with two conditions: the function has real profile data, and -precise-rotation-cost flag is turned on. This is not convenient for developers to experiment when profile is not available. Add a new option to force the new rotation algorithm -force-precise-rotation-cost llvm-svn: 269266
* Fix a bug when hoist spill to a BB with landingpad successor.Wei Mi2016-05-111-6/+10
| | | | | | | | | | | | | | | This is to fix the bug in https://llvm.org/bugs/show_bug.cgi?id=27612. When spill is hoisted to a BB with landingpad successor, and if the VNI of the spill reg lives into the landingpad successor, the spill should be inserted before the call which may throw exception. InsertPointAnalysis is used to compute the safe insert point. http://reviews.llvm.org/D20027 is a preparing patch for this patch. Differential Revision: http://reviews.llvm.org/D19884. llvm-svn: 269249
* [NFC] Extract LastSplitPoint computation from SplitAnalysis to a new classWei Mi2016-05-112-64/+101
| | | | | | | | | | | | InsertPointAnalysis. Because both split and spill hoisting want to use LastSplitPoint computation result, extract the LastSplitPoint computation from SplitAnalysis class which also contains a bunch of other analysises only related to split. Differential Revision: http://reviews.llvm.org/D20027. llvm-svn: 269248
* MachineVerifier: Fix error reporting.Matthias Braun2016-05-111-4/+10
| | | | | | | Do not use getVRegDef() to print "the definition" of a vreg. If there are multiple or none the function will fail. llvm-svn: 269239
* SDAG: Have SelectNodeTo replace uses if it CSE's instead of morphing a nodeJustin Bogner2016-05-112-9/+8
| | | | | | | | It's awkward to force callers of SelectNodeTo to figure out whether the node was morphed or CSE'd. Update uses here instead of requiring callers to (sometimes) do it. llvm-svn: 269235
* Return a StringRef from getSection.Rafael Espindola2016-05-111-1/+1
| | | | | | This is similar to how getName is handled. llvm-svn: 269218
* Refactor CodeView type records to use common code.Zachary Turner2016-05-111-2/+2
| | | | | | | Differential Revision: http://reviews.llvm.org/D20138 Reviewed By: rnk llvm-svn: 269216
* fix typos in comments; NFCSanjay Patel2016-05-111-41/+40
| | | | llvm-svn: 269206
* Merge two unreachable cases.Rafael Espindola2016-05-111-2/+1
| | | | llvm-svn: 269189
* SDAG: Make SelectCodeCommon return voidJustin Bogner2016-05-101-25/+41
| | | | | | | | | | | This means SelectCode unconditionally returns nullptr now. I'll follow up with a change to make that return void as well, but it seems best to keep that one very mechanical. This is part of the work to have Select return void instead of an SDNode *, which is in turn part of llvm.org/pr26808. llvm-svn: 269136
* ScheduleDAGInstrs: Comment on why subreg defs are not seen as uses; NFCMatthias Braun2016-05-101-0/+4
| | | | | | | | Usually subregister definitions are consider uses of the remaining lanes that did not get defined. Add a comment why the code in ScheduleDAGInstrs does not add use dependencies regardless. llvm-svn: 269107
* Debug Info: Prevent DW_AT_abstract_origin from being emitted twiceAdrian Prantl2016-05-101-7/+0
| | | | | | | | | | | | for the same subprogram. This fixes a bug where DW_AT_abstract_origin is being emitted twice for the same subprogram if a function is both inlined and emitted in the same translation unit, by restoring the pre-r266446 behavior. http://reviews.llvm.org/D20072 llvm-svn: 269103
* Fix PR26655: Bail out if all regs of an inst BUNDLE have the correct kill flagMandeep Singh Grang2016-05-102-27/+18
| | | | | | | | | | | | | | | | | | | | Summary: While setting kill flags on instructions inside a BUNDLE, we bail out as soon as we set kill flag on a register. But we are missing a check when all the registers already have the correct kill flag set. We need to bail out in that case as well. This patch refactors the old code and simply makes use of the addRegisterKilled function in MachineInstr.cpp in order to determine whether to set/remove kill on an instruction. Reviewers: apazos, t.p.northover, pete, MatzeB Subscribers: MatzeB, davide, llvm-commits Differential Revision: http://reviews.llvm.org/D17356 llvm-svn: 269092
* [ScheduleDAG] Make sure to process all def operands before any use operandsKrzysztof Parzyszek2016-05-101-8/+25
| | | | | | | | | | | | | | | | | An example from Hexagon where things went wrong: %R0<def> = L2_loadrigp <ga:@fp04> ; load function address J2_callr %R0<kill>, ..., %R0<imp-def> ; call *R0, return value in R0 ScheduleDAGInstrs::buildSchedGraph would visit all instructions going backwards, and in each instruction it would visit all operands in their order on the operand list. In the case of this call, it visited the use of R0 first, then removed it from the set Uses after it visited the def. This caused the DAG to be missing the data dependence edge on R0 between the load and the call. Differential Revision: http://reviews.llvm.org/D20102 llvm-svn: 269076
* [PR27599] [SystemZ] [SelectionDAG] Fix extension of atomic cmpxchg result.Marcin Koscielnicki2016-05-101-4/+17
| | | | | | | | | | | | Currently, SelectionDAG assumes 8/16-bit cmpxchg returns either a sign extended result, or a zero extended result. SystemZ takes a third option by returning junk in the high bits (rotated contents of the other bytes in the memory word). In that case, don't use Assert*ext, and zero-extend the result ourselves if a comparison is needed. Differential Revision: http://reviews.llvm.org/D19800 llvm-svn: 269075
* [foldMemoryOperand()] Pass LiveIntervals to enable liveness check.Jonas Paulsson2016-05-103-7/+9
| | | | | | | | | | | | | | | SystemZ (and probably other targets as well) can fold a memory operand by changing the opcode into a new instruction that as a side-effect also clobbers the CC-reg. In order to do this, liveness of that reg must first be checked. When LIS is passed, getRegUnit() can be called on it and the right LiveRange is computed on demand. Reviewed by Matthias Braun. http://reviews.llvm.org/D19861 llvm-svn: 269026
* LiveIntervalAnalysis: Rework constructMainRangeFromSubranges()Matthias Braun2016-05-104-246/+48
| | | | | | | | | | | | | | | | | | We now use LiveRangeCalc::extendToUses() instead of a specially designed algorithm in constructMainRangeFromSubranges(): - The original motivation for constructMainRangeFromSubranges() were differences between the main liverange and subranges because of hidden dead definitions. This case however cannot happen anymore with the DetectDeadLaneMasks pass in place. - It simplifies the code. - This fixes a longstanding bug where we did not properly create new SSA values on merging control flow (the MachineVerifier missed most of these cases). - Move constructMainRangeFromSubranges() to LiveIntervalAnalysis and LiveRangeCalc to better match the implementation/available helper functions. llvm-svn: 269016
* LiveInterval: Avoid unnecessary auto, add const; NFCMatthias Braun2016-05-101-3/+3
| | | | llvm-svn: 269015
* TargetPassConfig: Set PrintMachineCode even if addMachinePasses() does not run.Matthias Braun2016-05-101-5/+5
| | | | llvm-svn: 269013
* [WebAssembly] Move register stackification and coloring to a late phase.Dan Gohman2016-05-101-1/+1
| | | | | | | | | | | | | | | | | | | Move the register stackification and coloring passes to run very late, after PEI, tail duplication, and most other passes. This means that all code emitted and expanded by those passes is now exposed to these passes. This also eliminates the need for prologue/epilogue code to be manually stackified, which significantly simplifies the code. This does require running LiveIntervals a second time. It's useful to think of these late passes not as late optimization passes, but as a domain-specific compression algorithm based on knowledge of liveness information. It's used to compress the code after all conventional optimizations are complete, which is why it uses LiveIntervals at a phase when actual optimization passes don't typically need it. Differential Revision: http://reviews.llvm.org/D20075 llvm-svn: 269012
* CodeGen: Move TargetPassConfig from Passes.h to an own header; NFCMatthias Braun2016-05-106-3/+13
| | | | | | | | Many files include Passes.h but only a fraction needs to know about the TargetPassConfig class. Move it into an own header. Also rename Passes.cpp to TargetPassConfig.cpp while we are at it. llvm-svn: 269011
* PrologEpilogInserter: Remove unnecessary dependencyMatthias Braun2016-05-101-2/+0
| | | | llvm-svn: 269010
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