| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 92099
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SDISel. This optimization was causing simplifylibcalls to
introduce type-unsafe nastiness. This is the first step, I'll be
expanding the memcmp optimizations shortly, covering things that
we really really wouldn't want simplifylibcalls to do.
llvm-svn: 92098
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llvm-svn: 92097
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llvm-svn: 92096
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llvm-svn: 92094
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llvm-svn: 92093
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llvm-svn: 92011
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Patch by Sylve`re Teissier (sorry, ASCII only).
llvm-svn: 91988
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lowering code and update testcases.
llvm-svn: 91979
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llvm-svn: 91971
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llvm-svn: 91961
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llvm-svn: 91958
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llvm-svn: 91953
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llvm-svn: 91949
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llvm-svn: 91945
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is finished.
llvm-svn: 91942
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was using "Tmp1" in the first getNode call instead of Node->getOperand(0).
llvm-svn: 91936
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These checks would often trigger on unreachable statements inserted by
bugpoint, leading it astray.
It would be nice if we could distinguish unreachable blocks from errors.
llvm-svn: 91923
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ARM uses these to indicate predicates.
llvm-svn: 91922
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llvm-svn: 91920
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"indirect" operand is not a pointer.
llvm-svn: 91913
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return partial registers. This affected the back-end lowering code some.
Also patch up some places I missed before in the "get" functions.
llvm-svn: 91880
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llvm-svn: 91876
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generic copy functions.
llvm-svn: 91872
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llvm-svn: 91866
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llvm-svn: 91863
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SDNodes. This time in the load/store and limited-precision code.
llvm-svn: 91860
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This fixes an in-place update bug where code inserted at the end of basic blocks may not be covered by existing intervals which were live across the entire block. It is also consistent with the way ranges are specified for live intervals.
llvm-svn: 91859
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assign the ordering when called. Combine some of the ordering assignments to
keep things simple.
llvm-svn: 91857
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orderings to values returned by getValue().
llvm-svn: 91850
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shuffle and insert vector.
llvm-svn: 91847
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llvm-svn: 91846
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- Modify the "dump" method to emit the order of an SDNode.
llvm-svn: 91845
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a lot of the branching instructions.
llvm-svn: 91838
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llvm-svn: 91834
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by allowing backends to override routines that will default
the JIT and Static code generation to an appropriate code model
for the architecture.
Should fix PR 5773.
llvm-svn: 91824
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llvm-svn: 91764
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llvm-svn: 91744
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- Move DisableScheduling flag into TargetOption.h
- Move SDNodeOrdering into its own header file. Give it a minimal interface that
doesn't conflate construction with storage.
- Move assigning the ordering into the SelectionDAGBuilder.
This isn't used yet, so there should be no functional changes.
llvm-svn: 91727
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llvm-svn: 91717
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contains another loop, or an instruction. The loop form is
substantially more efficient on large loops than the typical
code it replaces.
llvm-svn: 91654
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The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types. Radar 7457110.
llvm-svn: 91649
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llvm-svn: 91636
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llvm-svn: 91635
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non-landing pad basic block as the successor to a block that ends in an
unconditional jump will cause block folding to remove the added block as a
successor. Thus eventually removing it AND the landing pad entirely. Critical
edge splitting is an optimization, so we can safely turn it off when dealing
with landing pads.
llvm-svn: 91634
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$ svn merge -c -91337 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r91337 into '.':
U lib/CodeGen/AsmPrinter/DwarfException.cpp
llvm-svn: 91618
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LegalizeDAG.cpp. Unlike the code it replaces, which simply decrements the simple
type by one, getHalfSizedIntegerVT() searches for the smallest simple integer
type that is at least half the size of the type it is called on. This approach
has the advantage that it will continue working if a new value type (such as
i24) is added to MVT.
Also, in preparation for new value types, remove the assertions that
non-power-of-2 8-bit-mutiple types are Extended when legalizing extload and
truncstore operations.
llvm-svn: 91614
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llvm-svn: 91604
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introduced a non-deterministic behavior in the optimizer somewhere.
llvm-svn: 91598
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llvm-svn: 91584
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