summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
Commit message (Collapse)AuthorAgeFilesLines
...
* Update comment for r149070.Chad Rosier2012-01-261-3/+1
| | | | llvm-svn: 149075
* Replace the use of isPredicable() with isPredicated() inChad Rosier2012-01-261-3/+2
| | | | | | | | | MachineBasicBlock::canFallThrough(). We're interested in the state of the instruction (i.e., is this a barrier or not?), not if the instruction is predicable or not. rdar://10501092 llvm-svn: 149070
* Clear kill flags before propagating a copy.Jakob Stoklund Olesen2012-01-262-1/+20
| | | | | | | | | | The live range of the source register may be extended when a redundant copy is eliminated. Make sure any kill flags between the two copies are cleared. This fixes PR11765. llvm-svn: 149069
* Add support for the R_ARM_TARGET1 relocation, which should be given to ↵James Molloy2012-01-261-1/+1
| | | | | | | | relocations applied to all C++ constructors and destructors. This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against. llvm-svn: 149057
* eliminate the Constant::getVectorElements method. There are better (andChris Lattner2012-01-261-13/+4
| | | | | | | more robust) ways to do what it was doing now. Also, add static methods for decoding a ShuffleVector mask. llvm-svn: 149028
* Improve sub-register def handling in ProcessImplicitDefs.Jakob Stoklund Olesen2012-01-251-9/+10
| | | | | | | | | This boils down to using MachineOperand::readsReg() more. This fixes PR11829 where a use ended up after the first def when lowering REG_SEQUENCE instructions involving IMPLICIT_DEFs. llvm-svn: 148996
* Properly emit ctors / dtors with priorities into desired sectionsAnton Korobeynikov2012-01-252-22/+43
| | | | | | | | and let linker handle the rest. This finally fixes PR5329 llvm-svn: 148990
* Don't add live ranges for aliases of physregs that are live in to theLang Hames2012-01-251-5/+0
| | | | | | | | function. They don't appear to be used, and are inconsistent with handling of other physreg intervals (i.e. intervals that are not live-in) where ranges are not inserted for aliases. llvm-svn: 148986
* Always break upon finding a vreg operand (in Release as well as +Asserts). ↵Lang Hames2012-01-251-6/+1
| | | | | | Remove assertion which can no longer trigger. llvm-svn: 148984
* use ConstantVector::getSplat in a few places.Chris Lattner2012-01-251-1/+1
| | | | llvm-svn: 148929
* Use the right method to get the # elements in a CDS.Chris Lattner2012-01-252-4/+4
| | | | llvm-svn: 148897
* Set correct <def,undef> flags when lowering REG_SEQUENCE.Jakob Stoklund Olesen2012-01-241-0/+46
| | | | | | | | | | | | | | | | | | | | A REG_SEQUENCE instruction is lowered into a sequence of partial defs: %vreg7:ssub_0<def,undef> = COPY %vreg20:ssub_0 %vreg7:ssub_1<def> = COPY %vreg2 %vreg7:ssub_2<def> = COPY %vreg2 %vreg7:ssub_3<def> = COPY %vreg2 The first def needs an <undef> flag to indicate it is the beginning of the live range, while the other defs are read-modify-write. Previously, we depended on LiveIntervalAnalysis to notice and fix the missing <def,undef>, but that solution was never robust, it was causing problems with ProcessImplicitDefs and the lowering of chained REG_SEQUENCE instructions. This fixes PR11841. llvm-svn: 148879
* Use the standard MachineFunction::print() after SlotIndexes.Jakob Stoklund Olesen2012-01-241-1/+1
| | | | llvm-svn: 148878
* Fix old doxygen comment.Jakob Stoklund Olesen2012-01-241-2/+1
| | | | llvm-svn: 148825
* add more support for ConstantDataSequentialChris Lattner2012-01-241-2/+19
| | | | llvm-svn: 148802
* An option to selectively enable part of ARM EHABI support.Evgeniy Stepanov2012-01-241-5/+14
| | | | | | | | This change adds an new option --arm-enable-ehabi-descriptors that enables emitting unwinding descriptors. This provides a mode with a working backtrace() without the (currently broken) exception support. llvm-svn: 148800
* Bit pack DIE structures better.Benjamin Kramer2012-01-241-23/+23
| | | | | | 16 bits are sufficient to store attributes, tags and forms. llvm-svn: 148799
* Remove generation of DW_AT_sibling. Nothing as far as I can tell uses it.Eric Christopher2012-01-243-26/+0
| | | | | | | | Saves about 1.5% on debug info size. rdar://10278198 llvm-svn: 148794
* Add AsmPrinter (aka MCLowering) support for ConstantDataSequential, Chris Lattner2012-01-241-32/+91
| | | | | | | | and clean up some other misc stuff. Unlike ConstantArray, we will prefer to emit .fill directives for "String" arrays that all have the same value, since they are denser than emitting a .ascii llvm-svn: 148793
* Preserve <def,undef> flags in CoalesceExtSubRegs.Jakob Stoklund Olesen2012-01-241-3/+7
| | | | | | | This won't have an effect until EliminateRegSequences() starts setting the undef flags. llvm-svn: 148779
* Revert r148686 (and r148694, a fix to it) due to a serious layeringChandler Carruth2012-01-241-20/+5
| | | | | | | | | | | | | | | | | | violation -- MC cannot depend on CodeGen. Specifically, the MCTargetDesc component of each target is actually a subcomponent of the MC library. As such, it cannot depend on the target-independent code generator, because MC itself cannot depend on the target-independent code generator. This change moved a flag from the ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in ARMException.cpp, leaving behind an 'extern' to refer back to it. That layering order isn't viable givin the constraints outlined above. Commandline flags are designed to be static specifically to avoid these types of bugs. Fixing this is likely going to require some non-trivial refactoring. llvm-svn: 148759
* Remove extraneous ';'s.Bill Wendling2012-01-231-1/+1
| | | | llvm-svn: 148740
* copyImplicitOps is redundant here - the loop above already copies these ops.Lang Hames2012-01-231-1/+0
| | | | llvm-svn: 148725
* Fix PR11829. PostRA LICM was too aggressive.Jakob Stoklund Olesen2012-01-231-4/+4
| | | | | | This fixes a typo in r148589. llvm-svn: 148724
* Simplify debug output.Jakob Stoklund Olesen2012-01-231-10/+2
| | | | llvm-svn: 148723
* An option to selectively enable parts of ARM EHABI support.Evgeniy Stepanov2012-01-231-5/+20
| | | | | | | | This change adds an new value to the --arm-enable-ehabi option that disables emitting unwinding descriptors. This mode gives a working backtrace() without the (currently broken) exception support. llvm-svn: 148686
* Add an option to disable buggy copy propagation passAnton Korobeynikov2012-01-221-1/+3
| | | | llvm-svn: 148662
* Fix an obvious typo.Evan Cheng2012-01-211-1/+1
| | | | llvm-svn: 148622
* Handle register masks in LiveVariables.Jakob Stoklund Olesen2012-01-211-0/+30
| | | | | | | | | | | A register mask operand kills any live physreg that isn't preserved. Unlike an implicit-def operand, the clobbered physregs are never live afterwards. This means LiveVariables has to track a much smaller number of live physregs, and it should spend much less time in addRegisterDead(). llvm-svn: 148609
* Delete an unused member variable.Jakob Stoklund Olesen2012-01-202-2/+0
| | | | llvm-svn: 148594
* Support register masks in MachineLICM.Jakob Stoklund Olesen2012-01-201-23/+36
| | | | | | Only PostRA LICM is affected. llvm-svn: 148589
* Handle register masks in DeadMachineInstructionElim.Jakob Stoklund Olesen2012-01-201-0/+7
| | | | | | Don't track live physregs that are clobbered by a register mask operand. llvm-svn: 148588
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-2015-46/+12
| | | | llvm-svn: 148578
* Extend Attributes to 64 bitsKostya Serebryany2012-01-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Problem: LLVM needs more function attributes than currently available (32 bits). One such proposed attribute is "address_safety", which shows that a function is being checked for address safety (by AddressSanitizer, SAFECode, etc). Solution: - extend the Attributes from 32 bits to 64-bits - wrap the object into a class so that unsigned is never erroneously used instead - change "unsigned" to "Attributes" throughout the code, including one place in clang. - the class has no "operator uint64 ()", but it has "uint64_t Raw() " to support packing/unpacking. - the class has "safe operator bool()" to support the common idiom: if (Attributes attr = getAttrs()) useAttrs(attr); - The CTOR from uint64_t is marked explicit, so I had to add a few explicit CTOR calls - Add the new attribute "address_safety". Doing it in the same commit to check that attributes beyond first 32 bits actually work. - Some of the functions from the Attribute namespace are worth moving inside the class, but I'd prefer to have it as a separate commit. Tested: "make check" on Linux (32-bit and 64-bit) and Mac (10.6) built/run spec CPU 2006 on Linux with clang -O2. This change will break clang build in lib/CodeGen/CGCall.cpp. The following patch will fix it. llvm-svn: 148553
* When lowering the 'resume' instruction, look to see if we can eliminate theBill Wendling2012-01-201-2/+32
| | | | | | | | 'insertvalue' instructions that recreate the structure returned by the 'landingpad' instruction. Because the 'insertvalue' instruction isn't supported by FastISel, this can save a bit of time during -O0 compilation. llvm-svn: 148520
* More bundle related API additions.Evan Cheng2012-01-191-1/+52
| | | | llvm-svn: 148465
* Rewriter should definitly rewrite instructions inside bundles.Evan Cheng2012-01-191-2/+2
| | | | llvm-svn: 148464
* Enhance finalizeBundle to return end of bundle iterator because it makes sense.Evan Cheng2012-01-191-3/+6
| | | | llvm-svn: 148462
* - Slight change to finalizeBundle() interface. LastMI is not exclusive (pointingEvan Cheng2012-01-191-3/+18
| | | | | | | | | | | to instruction right after the last instruction in the bundle. - Add a finalizeBundle() variant that doesn't specify LastMI. Instead, the code will find the last instruction in the bundle by following the 'InsideBundle' marker. This is useful in case bundles are formed early (i.e. during MI scheduling) but finalized later (i.e. after register allocator has finished rewriting virtual registers with physical registers). llvm-svn: 148444
* Rename Finalizebundle to finalizeBundle to conform to coding guideline.Evan Cheng2012-01-191-2/+2
| | | | llvm-svn: 148440
* Add a RegisterMaskSDNode class.Jakob Stoklund Olesen2012-01-184-2/+22
| | | | | | | | | | | This SelectionDAG node will be attached to call nodes by LowerCall(), and eventually becomes a MO_RegisterMask MachineOperand on the MachineInstr representing the call instruction. LowerCall() will attach a register mask that depends on the calling convention. llvm-svn: 148436
* Fixed macro condition.Lang Hames2012-01-181-1/+1
| | | | llvm-svn: 148408
* Fix a bug in the type-legalization of vector integers. When we bitcast one ↵Nadav Rotem2012-01-181-2/+4
| | | | | | vector type to another, we must not bitcast the result if one type is widened while the other is promoted. llvm-svn: 148383
* Fix ISD::REG_SEQUENCE to accept physical registers and change ↵Pete Cooper2012-01-182-16/+24
| | | | | | TwoAddressInstructionPass to insert copies for any physical reg operands of the REG_SEQUENCE llvm-svn: 148377
* Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.Nadav Rotem2012-01-171-4/+35
| | | | llvm-svn: 148337
* Teach DAG combiner to turn a BUILD_VECTOR of UNDEFs into an UNDEF of vector ↵Craig Topper2012-01-171-4/+8
| | | | | | type. llvm-svn: 148297
* misched: Inital interface and implementation for ScheduleTopDownLive and ↵Andrew Trick2012-01-171-17/+130
| | | | | | ShuffleInstructions. llvm-svn: 148291
* Renamed MachineScheduler to ScheduleTopDownLive.Andrew Trick2012-01-174-51/+63
| | | | | | Responding to code review. llvm-svn: 148290
* Moving options declarations around.Andrew Trick2012-01-172-2/+7
| | | | | | More short term hackery until we have a way to configure passes that work on LiveIntervals. llvm-svn: 148289
* Add 148175 back. I am unable to reproduce any non determinism in a dragoneggRafael Espindola2012-01-171-2/+4
| | | | | | | | | | | or clang bootstrap. I will keep an eye on the bots. Original message: Only emit the Leh_func_endN symbol when needed. llvm-svn: 148283
OpenPOWER on IntegriCloud