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* [SelectionDAG] ComputeKnownBits - add support for SMIN+SMAX clamp patternsSimon Pilgrim2018-02-191-5/+32
| | | | | | | | | | If we have a clamp pattern, SMIN(SMAX(X, LO),HI) or SMAX(SMIN(X, HI),LO) then we can deduce that the number of signbits (zeros/ones) will be at least the minimum of the LO and HI constants. ComputeKnownBits equivalent of D43338. Differential Revision: https://reviews.llvm.org/D43463 llvm-svn: 325521
* [CodeGen] Refactor AppleAccelTablePavel Labath2018-02-193-155/+242
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This commit separates the abstract accelerator table data structure from the code for writing out an on-disk representation of a specific accelerator table format. The idea is that former (now called AccelTable<T>) can be reused for the DWARF v5 accelerator tables as-is, without any further customizations. Some bits of the emission code (now living in the EmissionContext class) can be reused for DWARF v5 as well, but the subtle differences in the layout of various subtables mean the sharing is not always possible. (Also, the individual emit*** functions are fairly simple so there's a tradeoff between making a bigger general-purpose function, and two smaller targeted functions.) Another advantage of this setup is that more of the serialization logic can be hidden in the .cpp file -- I have moved declarations of the header and all the emission functions there. Reviewers: JDevlieghere, aprantl, probinson, dblaikie Subscribers: echristo, clayborg, vleschuk, llvm-commits Differential Revision: https://reviews.llvm.org/D43285 llvm-svn: 325516
* [CodeGen] Fix tests breaking after r325505Francis Visoiu Mistrih2018-02-191-2/+0
| | | | llvm-svn: 325512
* Revert "[CodeGen] Move printing '\n' from MachineInstr::print to ↵Francis Visoiu Mistrih2018-02-194-13/+8
| | | | | | | | MachineBasicBlock::print" This reverts commit r324681. llvm-svn: 325505
* Fix Wparentheses warning. NFCISimon Pilgrim2018-02-171-1/+1
| | | | llvm-svn: 325451
* [SelectionDAG] ComputeNumSignBits - add support for SMIN+SMAX clamp patternsSimon Pilgrim2018-02-171-1/+26
| | | | | | | | | | If we have a clamp pattern, SMIN(SMAX(X, LO),HI) or SMAX(SMIN(X, HI),LO) then we can deduce that the number of signbits will be at least the minimum of the LO and HI constants. I haven't bothered with the UMIN/UMAX equivalent as (1) we don't have any current use cases and (2) I wonder if we'd be better off immediately falling back for ComputeKnownBits for UMIN/UMAX which already has optimization patterns useful for unsigned cases. Differential Revision: https://reviews.llvm.org/D43338 llvm-svn: 325450
* [SelectionDAG] SimplifyDemandedVectorElts - add support for VECTOR_INSERT_ELTSimon Pilgrim2018-02-171-0/+34
| | | | | | Differential Revision: https://reviews.llvm.org/D43431 llvm-svn: 325449
* [DebugInfo][FastISel] Fix dropping dbg.value()Sander de Smalen2018-02-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Summary: https://llvm.org/PR36263 shows that when compiling at -O0 a dbg.value() instruction (that remains from an original dbg.declare()) is dropped by FastISel. Since FastISel selects instructions by iterating a basic block backwards, it drops the dbg.value if one of its operands is not yet instantiated by a previously selected instruction. Instead of calling 'lookUpRegForValue()' we can call 'getRegForValue()' instead that will insert a placeholder for the operand to be filled in when continuing the instruction selection. Reviewers: aprantl, dblaikie, probinson Reviewed By: aprantl Subscribers: llvm-commits, dstenb, JDevlieghere Differential Revision: https://reviews.llvm.org/D43386 llvm-svn: 325438
* [AArch64] Implement dynamic stack probing for windowsMartin Storsjo2018-02-171-0/+4
| | | | | | | | | This makes sure that alloca() function calls properly probe the stack as needed. Differential Revision: https://reviews.llvm.org/D42356 llvm-svn: 325433
* [DAGCombiner] Remove simplifyShuffleMask - now handled more generally by ↵Simon Pilgrim2018-02-171-35/+0
| | | | | | SimplifyDemandedVectorElts. llvm-svn: 325429
* [DebugInfo] Removed assert on missing CountVarDIESander de Smalen2018-02-171-7/+2
| | | | | | | | | | | | | | | | | | | | Summary: The assert for a DISubrange's CountVarDIE to be available fails when the dbg.value() has been optimized away for any reason. Having the assert for that is a little heavy, so instead removing it now in favor of not generating the 'count' expression. Addresses http://llvm.org/PR36263 . Reviewers: aprantl, dblaikie, probinson Reviewed By: aprantl Subscribers: JDevlieghere, llvm-commits, dstenb Differential Revision: https://reviews.llvm.org/D43387 llvm-svn: 325427
* Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding"Quentin Colombet2018-02-172-210/+1
| | | | | | | | | | | | | | | | | This reverts commit r323991. This commit breaks target that don't model all the register constraints in TableGen. So far the workaround was to set the hasExtraXXXRegAllocReq, but it proves that it doesn't cover all the cases. For instance, when mutating an instruction (like in the lowering of COPYs) the isRenamable flag is not properly updated. The same problem will happen when attaching machine operand from one instruction to another. Geoff Berry is working on a fix in https://reviews.llvm.org/D43042. llvm-svn: 325421
* [DAG, X86] Revert r324797, r324491, and r324359.Chandler Carruth2018-02-171-79/+215
| | | | | | | | | | | | Sadly, r324359 caused at least PR36312. There is a patch out for review but it seems to be taking a bit and we've already had these crashers in tree for too long. We're hitting this PR in real code now and are blocked on shipping new compilers as a consequence so I'm reverting us back to green. Sorry for the churn due to the stacked changes that I had to revert. =/ llvm-svn: 325420
* Fix signed/unsigned comparison warning. NFCI.Simon Pilgrim2018-02-161-1/+1
| | | | llvm-svn: 325363
* Fix signed/unsigned comparison warning. NFCI.Simon Pilgrim2018-02-161-3/+3
| | | | llvm-svn: 325359
* [SelectionDAG] Enable SimplifyDemandedVectorElts support for simplifying ↵Simon Pilgrim2018-02-161-0/+25
| | | | | | | | | | shuffle masks Based off the DemandedElts mask the and UNDEF elements returned from the SimplifyDemandedVectorElts calls to the shuffle operands, we can attempt to simplify the shuffle mask. I had to be very conservative here as accepting post-legalized shuffle masks could cause problems for targets that legalize UNDEF mask elements back to inrange values (PowerPC), similarly combining to identity shuffle masks could cause too much UNDEF information to disappear for later combines. llvm-svn: 325354
* [SelectionDAG] Add initial SimplifyDemandedVectorElts support for ↵Simon Pilgrim2018-02-161-0/+20
| | | | | | | | simplifying VSELECT operands This just adds a basic pass through - we can add constant selection mask handling in a future patch to fully match InstCombine. llvm-svn: 325338
* [LegalizeDAG] Fix legalization of SETCCMikhail Maltsev2018-02-161-1/+1
| | | | | | | | | | | | | | | | | | | Summary: Currently when expanding a SETCC node into a SELECT_CC, LLVM uses an incorrect type for determining BooleanContent of the result. This patch fixes the issue. Fixes PR36079. Reviewers: rogfer01, javed.absar, efriedma Reviewed By: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D43282 llvm-svn: 325325
* [DAGCombiner] Call ExtendUsesToFormExtLoad in (zext (and (load)))->(and ↵Craig Topper2018-02-151-13/+14
| | | | | | | | | | | | | | (zextload)) even when the and does not have multiple uses Same for the sign extend case. Currently we check for multiple uses on the binop. Then we call ExtendUsesToFormExtLoad to capture SetCCs that use the load. So we only end up finding any setccs when the and has additional uses and the load is used by a setcc. I don't think the and having multiple uses is relevant here. I think we should only be checking for the load having multiple uses. This changes an NVPTX test because we now find that the load has a second use by a truncate, but ExtendUsesToFormExtLoad only looks at setccs it can extend. All other operations just check isTruncateFree. Maybe we should allow widening of an existing truncate even if its not free? Differential Revision: https://reviews.llvm.org/D43063 llvm-svn: 325289
* [CodeGen] Separate MBB metadata from instructions in -debug printingFrancis Visoiu Mistrih2018-02-151-1/+9
| | | | | | | Add an empty line after 'liveins:', 'successors:', or '; predecessors:', the one that ends up to be the last one. llvm-svn: 325258
* [SelectionDAG] Pull out repeated Op.getOpcode(). NFCI.Simon Pilgrim2018-02-151-6/+7
| | | | llvm-svn: 325253
* [CodeGen] Print irreducible loop header weight as a MIR commentFrancis Visoiu Mistrih2018-02-151-3/+2
| | | | | | Prefix it with '; ' to make it more MIR-compatible. llvm-svn: 325251
* [DebugInfo] Accept enumeration types without underlying integer type present inMomchil Velikov2018-02-151-5/+5
| | | | | | | | | | debug info metadata ... when generating DWARF. Differential Revision: https://reviews.llvm.org/D43304 llvm-svn: 325234
* [SelectionDAG] Add initial implementation of ↵Simon Pilgrim2018-02-152-91/+238
| | | | | | | | | | | | TargetLowering::SimplifyDemandedVectorElts This is mainly a move of simplifyShuffleOperands from DAGCombiner::visitVECTOR_SHUFFLE to create a more general purpose TargetLowering::SimplifyDemandedVectorElts implementation. Further features can be moved/added in future patches. Differential Revision: https://reviews.llvm.org/D42896 llvm-svn: 325232
* Revert r325224 "Report fatal error in the case of out of memory"Serge Pavlov2018-02-153-5/+4
| | | | | | It caused fails on some buildbots. llvm-svn: 325227
* Report fatal error in the case of out of memorySerge Pavlov2018-02-153-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Analysis of fails in the case of out of memory errors can be tricky on Windows. Such error emerges at the point where memory allocation function fails, but manifests itself when null pointer is used. These two points may be distant from each other. Besides, next runs may not exhibit allocation error. Usual programming practice does not require checking result of 'operator new' because it throws 'std::bad_alloc' in the case of allocation error. However, LLVM is usually built with exceptions turned off, so 'new' can return null pointer. This change installs custom new handler, which causes fatal error in the case of out of memory. The handler is installed automatically prior to call to 'main' during construction of a static object defined in 'lib/Support/ErrorHandling.cpp'. If the application does not use this file, the handler may be installed manually by a call to 'llvm::install_out_of_memory_new_handler', declared in 'include/llvm/Support/ErrorHandling.h". There are calls to C allocation functions, malloc, calloc and realloc. They are used for interoperability with C code, when allocated object has variable size and when it is necessary to avoid call of constructors. In many calls the result is not checked against null pointer. To simplify checks, new functions are defined in the namespace 'llvm' with the same names as these C function. These functions produce fatal error if allocation fails. User should use 'llvm::malloc' instead of 'std::malloc' in order to use the safe variant. This change replaces 'std::malloc' in the cases when the result of allocation function is not checked against null pointer. Finally, there are plain C code, that uses malloc and similar functions. If the result is not checked, assert statements are added. Differential Revision: https://reviews.llvm.org/D43010 llvm-svn: 325224
* (NFC)[MachineCombiner] Improve debug output.Andrew V. Tischenko2018-02-151-28/+53
| | | | llvm-svn: 325217
* [CodeGen] Print predecessors, successors, then liveins in -debug printingFrancis Visoiu Mistrih2018-02-141-17/+18
| | | | | | | | Reorder them to match MIR. Predecessors are only comments, and they're not usually printed in MIR. llvm-svn: 325166
* GlobalISel: Add templated functions and pattern matcher support for some ↵Volkan Keles2018-02-141-11/+7
| | | | | | | | | | | | | | | | | | more opcodes Summary: This patch adds templated functions to MachineIRBuilder for some opcodes and adds pattern matcher support for G_AND and G_OR. Reviewers: aditya_nandakumar Reviewed By: aditya_nandakumar Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D43309 llvm-svn: 325162
* Pass a reference to a module to the bitcode writer.Rafael Espindola2018-02-141-2/+2
| | | | | | | This simplifies most callers as they are already using references or std::unique_ptr. llvm-svn: 325155
* [RegisterClassInfo] Invalidate the register pressure set limit cache when ↵Craig Topper2018-02-141-4/+5
| | | | | | | | | | | | | | reserved regs or callee saved regs change Previously we only invalidated the pressure set limit cached when the TargetRegisterInfo pointer changes. But as reserved regs and callee saved regs are used as part of calculating the limits we should invalidate when those change too. I encountered this when reverting a patch from the 6.0 branch. One of the x86 test files had a function that used rbp as a frame pointer, making it reserved. It was followed by another function which didn't use rbp but had the same TRI so the pressure set limit cache was not invalidated. If i removed the function that used rbp as a frame pointer from the file, the remaining function then got a different register pressure limit for the GR16 pressure set. This caused the machine scheduler to change the scheduling for the function. This was an unexpected change from just deleting a function. I don't have a test case for trunk because the particular x86 test case is different enough from the 6.0 branch to not be affected now. Differential Revision: https://reviews.llvm.org/D43274 llvm-svn: 325153
* [DWARF] Fix incorrect prologue end line record.Paul Robinson2018-02-141-1/+3
| | | | | | | | | | | | The prologue-end line record must be emitted after the last instruction that is part of the function frame setup code and before the instruction that marks the beginning of the function body. Patch by Carlos Alberto Enciso! Differential Revision: https://reviews.llvm.org/D41762 llvm-svn: 325143
* [SelectionDAG][X86] Fix incorrect offset generated for VMASKMOVAlexander Ivchenko2018-02-142-18/+21
| | | | | | | | When creating high MachineMemOperand for MSTORE/MLOAD we supply it with the original PointerInfo, while the pointer itself had been incremented. The patch adds the proper offset to the PointerInfo. llvm-svn: 325135
* [Utils] Salvage the debug info of DCE'ed 'and' instructionsPetar Jovanovic2018-02-141-0/+1
| | | | | | | | | | Preserve debug info from a dead 'and' instruction with a constant. Patch by Djordje Todorovic. Differential Revision: https://reviews.llvm.org/D43163 llvm-svn: 325119
* Adding a width of the GEP index to the Data Layout.Elena Demikhovsky2018-02-143-10/+9
| | | | | | | | | | | | | | | | | | Making a width of GEP Index, which is used for address calculation, to be one of the pointer properties in the Data Layout. p[address space]:size:memory_size:alignment:pref_alignment:index_size_in_bits. The index size parameter is optional, if not specified, it is equal to the pointer size. Till now, the InstCombiner normalized GEPs and extended the Index operand to the pointer width. It works fine if you can convert pointer to integer for address calculation and all registered targets do this. But some ISAs have very restricted instruction set for the pointer calculation. During discussions were desided to retrieve information for GEP index from the Data Layout. http://lists.llvm.org/pipermail/llvm-dev/2018-January/120416.html I added an interface to the Data Layout and I changed the InstCombiner and some other passes to take the Index width into account. This change does not affect any in-tree target. I added tests to cover data layouts with explicitly specified index size. Differential Revision: https://reviews.llvm.org/D42123 llvm-svn: 325102
* [SelectionDAG] Remove duplicate code from TargetLowering::SimplifySetCC.Craig Topper2018-02-141-4/+0
| | | | | | This exact code already exists a little further up. llvm-svn: 325101
* [globalisel][legalizerinfo] Follow up on post-commit review comments after ↵Daniel Sanders2018-02-131-0/+4
| | | | | | | | | | | | | | r323681 * Document most API's * Delete a useless function call * Fix a discrepancy between the single and multi-opcode variants of getActionDefinitions(). The multi-opcode variant now requires that more than one opcode is requested. Previously it acted much like the single-opcode form but unnecessarily enforced the requirements of the multi-opcode form. llvm-svn: 325067
* Document the shortcomings of DwarfExpression::addMachineReg().Adrian Prantl2018-02-131-4/+12
| | | | | | | | | | | | | Also make a drive-by-fix of a bug in the subregister scan code that only triggers with an incomplete or otherwise very irregular machine description. rdar://problem/37404493 This re-applies r324972 with an early exit in the case of a complete failure to make this commit NFC again as intended. llvm-svn: 325041
* [CodeGen] Print bundled instructions using the MIR syntax in -debug outputFrancis Visoiu Mistrih2018-02-131-7/+23
| | | | | | | | | | | | | | | | | Old syntax: BUNDLE implicit-def %r0, implicit-def %r1, implicit %r2 * %r0 = SOME_OP %r2 * %r1 = ANOTHER_OP internal %r0 New syntax: BUNDLE implicit-def %r0, implicit-def %r1, implicit %r2 { %r0 = SOME_OP %r2 %r1 = ANOTHER_OP internal %r0 } llvm-svn: 325032
* [DAGCombiner] Add one use check to fold (not (and x, y)) -> (or (not x), ↵Craig Topper2018-02-131-2/+2
| | | | | | | | | | | | | | | | | | | (not y)) Summary: If the and has an additional use we shouldn't invert it. That creates an additional instruction. While there add a one use check to the transform above that looked similar. Reviewers: spatel, RKSimon Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D43225 llvm-svn: 325019
* [DAG] fix type of undef returned by getNode()Sanjay Patel2018-02-131-2/+2
| | | | | | | | The bug has been lying dormant, but apparently was never exposed, until after rL324941 because we didn't return the correct result for shifts with undef operands. llvm-svn: 325010
* Revert "Document the shortcomings of DwarfExpression::addMachineReg()."Adrian Prantl2018-02-131-7/+3
| | | | | | | This reverts commit r324972. This commit broke a bot, so perhaps it is testable after all? llvm-svn: 324977
* [Utils] Salvage debug info of DCE'ed mul/sdiv/srem instructionsVedant Kumar2018-02-131-0/+2
| | | | | | | | | | | | | Here are the number of additional debug values salvaged in a stage2 build of clang: 63 SALVAGE: MUL 1250 SALVAGE: SDIV (No values were salvaged from `srem` instructions in this experiment, but it's a simple case to handle so we might as well.) llvm-svn: 324976
* [Utils] Salvage debug info of DCE'ed shl/lhsr/ashr instructionsVedant Kumar2018-02-131-0/+3
| | | | | | | | | | | Here are the number of additional debug values salvaged in a stage2 build of clang: 1912 SALVAGE: ASHR 405 SALVAGE: LSHR 249 SALVAGE: SHL llvm-svn: 324975
* [Utils] Salvage the debug info of DCE'ed 'xor' instructionsVedant Kumar2018-02-131-0/+1
| | | | | | | | This salvages 259 debug values in a stage2 build of clang. Differential Revision: https://reviews.llvm.org/D43207 llvm-svn: 324973
* Document the shortcomings of DwarfExpression::addMachineReg().Adrian Prantl2018-02-131-3/+7
| | | | | | | | | | Also make a drive-by-fix of a bug in the subregister scan code that only triggers with an incomplete or otherwise very irregular machine description. rdar://problem/37404493 llvm-svn: 324972
* GlobalISel: IRTranslate llvm.fmuladd.* intrinsicVolkan Keles2018-02-131-0/+19
| | | | | | | | | | | | Reviewers: qcolombet, ab, dsanders, aditya_nandakumar, bogner Reviewed By: qcolombet Subscribers: rovka, kristof.beyls, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D43090 llvm-svn: 324971
* [SafeStack] Use updated CreateMemCpy API to set more accurate source and ↵Daniel Neilson2018-02-123-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | destination alignments. Summary: This change is part of step five in the series of changes to remove alignment argument from memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the creation of memcpys in the SafeStack pass to set the alignment of the destination object to its stack alignment while separately setting the source byval arguments alignment to its alignment. Steps: Step 1) Remove alignment parameter and create alignment parameter attributes for memcpy/memmove/memset. ( rL322965, rC322964, rL322963 ) Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing source and dest alignments. ( rL323597 ) Step 3) Update Clang to use the new IRBuilder API. ( rC323617 ) Step 4) Update Polly to use the new IRBuilder API. ( rL323618 ) Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API, and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment() and [get|set]SourceAlignment() instead. (rL323886, rL323891, rL324148, rL324273, rL324278, rL324384, rL324395, rL324402, rL324626, rL324642, rL324653, rL324654, rL324773, rL324774, rL324781, rL324784 ) Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the MemIntrinsicInst::[get|set]Alignment() methods. Reference http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20151109/312083.html Reviewers: eugenis, bollu Reviewed By: eugenis Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42710 llvm-svn: 324955
* [DAG] make binops with undef operands consistent with IRSanjay Patel2018-02-121-20/+7
| | | | | | | | | | | | | | | | | | | | | This started by noticing that scalar and vector types were producing different results with div ops in PR36305: https://bugs.llvm.org/show_bug.cgi?id=36305 ...but the problem is bigger. I couldn't keep it straight without a table, so I'm attaching that as a PDF to the review. The x86 tests in undef-ops.ll correspond to that table. Green means that instsimplify and the DAG agree on the result for all types. Red means the DAG was returning undef when IR was not. Yellow means the DAG was returning a non-undef result when IR returned undef. This patch assumes that we're currently doing the right thing in IR. Note: I couldn't find any problems with lowering vector constants as the code comments were warning, but those comments were written long ago in rL36413 . Differential Revision: https://reviews.llvm.org/D43141 llvm-svn: 324941
* [GlobalMerge] Allow merging of dllexported variablesMartin Storsjo2018-02-121-3/+6
| | | | | | | | | If merging them, the dllexport attribute needs to be brought along to the new GlobalAlias. Differential Revision: https://reviews.llvm.org/D43192 llvm-svn: 324937
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