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* Recommit the fix for rdar://9289512 with a couple tweaks toChris Lattner2011-04-221-17/+54
| | | | | | | | | | | fix bugs exposed by the gcc dejagnu testsuite: 1. The load may actually be used by a dead instruction, which would cause an assert. 2. The load may not be used by the current chain of instructions, and we could move it past a side-effecting instruction. Change how we process uses to define the problem away. llvm-svn: 130018
* DAGCombine: fold "(zext x) == C" into "x == (trunc C)" if the trunc is lossless.Benjamin Kramer2011-04-221-0/+36
| | | | | | | | | | | | On x86 this allows to fold a load into the cmp, greatly reducing register pressure. movzbl (%rdi), %eax cmpl $47, %eax -> cmpb $47, (%rdi) This shaves 8k off gcc.o on i386. I'll leave applying the patch in README.txt to Chris :) llvm-svn: 130005
* Do not leak argument's DbgVariables.Devang Patel2011-04-221-1/+1
| | | | llvm-svn: 130004
* TypoEvan Cheng2011-04-221-1/+1
| | | | llvm-svn: 129970
* Branch folding is folding a landing pad into a regular BB.Bill Wendling2011-04-221-1/+1
| | | | | | | | | | | | | | | An exception is thrown via a call to _cxa_throw, which we don't expect to return. Therefore, the "true" part of the invoke goes to a BB that has 'unreachable' as its only instruction. This is lowered into an empty MachineBB. The landing pad for this invoke, however, is directly after the "true" MBB. When the empty MBB is removed, the landing pad is directly below the BB with the invoke call. The unconditional branch is removed and then the two blocks are merged together. The testcase is too big for a regression test. <rdar://problem/9305728> llvm-svn: 129965
* Refactor.Devang Patel2011-04-212-30/+35
| | | | llvm-svn: 129938
* Don't recycle loop variables.Matt Beaumont-Gay2011-04-211-1/+1
| | | | llvm-svn: 129928
* Allow allocatable ranges from global live range splitting to be split again.Jakob Stoklund Olesen2011-04-213-7/+45
| | | | | | | | | | | | | | | | | | | | | These intervals are allocatable immediately after splitting, but they may be evicted because of later splitting. This is rare, but when it happens they should be split again. The remainder intervals that cannot be allocated after splitting still move directly to spilling. SplitEditor::finish can optionally provide a mapping from new live intervals back to the original interval indexes returned by openIntv(). Each original interval index can map to multiple new intervals after connected components have been separated. Dead code elimination may also add existing intervals to the list. The reverse mapping allows the SplitEditor client to treat the new intervals differently depending on the split region they came from. llvm-svn: 129925
* Add comment in output stream.Devang Patel2011-04-211-0/+3
| | | | llvm-svn: 129921
* Revert r1296656, "Fix rdar://9289512 - not folding load into compare at -O0...",Daniel Dunbar2011-04-211-41/+15
| | | | | | which broke a couple GCC test suite tests at -O0. llvm-svn: 129914
* Add debug output for rematerializable instructions.Jakob Stoklund Olesen2011-04-203-6/+10
| | | | llvm-svn: 129883
* Permit remat when a virtual register has multiple defs.Jakob Stoklund Olesen2011-04-201-5/+0
| | | | | | | | TII::isTriviallyReMaterializable() shouldn't depend on any properties of the register being defined by the instruction. Rematerialization is going to create a new virtual register anyway. llvm-svn: 129882
* Prefer cheap registers for busy live ranges.Jakob Stoklund Olesen2011-04-202-6/+45
| | | | | | | | | | | | | | On the x86-64 and thumb2 targets, some registers are more expensive to encode than others in the same register class. Add a CostPerUse field to the TableGen register description, and make it available from TRI->getCostPerUse. This represents the cost of a REX prefix or a 32-bit instruction encoding required by choosing a high register. Teach the greedy register allocator to prefer cheap registers for busy live ranges (as indicated by spill weight). llvm-svn: 129864
* ARM byval support. Will be enabled by another patch to the FE. ↵Stuart Hastings2011-04-201-3/+4
| | | | | | <rdar://problem/7662569> llvm-svn: 129858
* Remove unused arguments.Rafael Espindola2011-04-202-5/+3
| | | | llvm-svn: 129844
* Rewrite the expander for umulo/smulo to remember to sign extend the inputEric Christopher2011-04-201-10/+58
| | | | | | | | | manually and pass all (now) 4 arguments to the mul libcall. Add a new ExpandLibCall for just this (copied gratuitously from type legalization). Fixes rdar://9292577 llvm-svn: 129842
* ADT/Triple: Renambe isOSX... methods to isMacOSX for consistency with the OSDaniel Dunbar2011-04-201-1/+1
| | | | | | triple component. llvm-svn: 129838
* CodeGen: Eliminate a use of getDarwinMajorNumber().Daniel Dunbar2011-04-191-11/+3
| | | | | | | | | - There is a minor semantic change here (evidenced by the test change) for Darwin triples that have no version component. I debated changing the default behavior of isOSVersionLT, but decided it made more sense for triples to be explicit. llvm-svn: 129802
* Delete unnecessary variable. <rdar://problem/7662569>Stuart Hastings2011-04-191-11/+4
| | | | llvm-svn: 129796
* Avoid write-after-write issue hazards for Cortex-A9.Bob Wilson2011-04-191-10/+24
| | | | | | | | | | | Add a avoidWriteAfterWrite() target hook to identify register classes that suffer from write-after-write hazards. For those register classes, try to avoid writing the same register in two consecutive instructions. This is currently disabled by default. We should not spill to avoid hazards! The command line flag -avoid-waw-hazard can be used to enable waw avoidance. llvm-svn: 129772
* Force the greedy register allocator to be linked alongside linear scan.Jakob Stoklund Olesen2011-04-191-0/+5
| | | | | | This means that the new register allocator can be used with 'clang -mllvm -regalloc=greedy'. llvm-svn: 129764
* SelectBasicBlock is rather slow even when it doesn't do anything; skip theEli Friedman2011-04-191-5/+7
| | | | | | unnecessary work where possible. llvm-svn: 129763
* Support nested CALLSEQ_BEGIN/END; necessary for ARM byval support. ↵Stuart Hastings2011-04-191-42/+56
| | | | | | <rdar://problem/7662569> llvm-svn: 129761
* Implement support for x86 fastisel of small fixed-sized memcpys, which are ↵Chris Lattner2011-04-191-52/+44
| | | | | | | | | generated en-mass for C++ PODs. On my c++ test file, this cuts the fast isel rejects by 10x and shrinks the generated .s file by 5% llvm-svn: 129755
* Simplify declarations slightly by using typedefs.Eli Friedman2011-04-181-4/+2
| | | | llvm-svn: 129720
* Reduce clutter in asm output. Do not emit source location as comment for ↵Devang Patel2011-04-182-30/+1
| | | | | | each instruction. llvm-svn: 129715
* Handle spilling around an instruction that has an early-clobber re-definition ofJakob Stoklund Olesen2011-04-181-14/+15
| | | | | | | | the spilled register. This is quite common on ARM now that some stores have early-clobber defines. llvm-svn: 129714
* Fix a bug where we were counting the alias sets as completely usedEric Christopher2011-04-181-5/+0
| | | | | | | | | registers for fast allocation a different way. This has us updating used registers only when we're using that exact register. Fixes rdar://9207598 llvm-svn: 129711
* while we're at it, handle 'sdiv exact' of a power of 2 also,Chris Lattner2011-04-181-0/+8
| | | | | | this fixes a few rejects on c++ iterator loops. llvm-svn: 129694
* fix rdar://9297011 - udiv by power of two causing fast-isel rejectsChris Lattner2011-04-181-0/+4
| | | | llvm-svn: 129693
* 1. merge fast-isel-shift-imm.ll into fast-isel-x86-64.llChris Lattner2011-04-171-18/+30
| | | | | | | | | | 2. implement rdar://9289501 - fast isel should fold trivial multiplies to shifts 3. teach tblgen to handle shift immediates that are different sizes than the shifted operands, eliminating some code from the X86 fast isel backend. 4. Have FastISel::SelectBinaryOp use (the poorly named) FastEmit_ri_ function instead of FastEmit_ri to simplify code. llvm-svn: 129666
* fix an oversight which caused us to compile the testcase (and otherChris Lattner2011-04-171-5/+3
| | | | | | | | | | | | | | | | | | | less trivial things) into a dummy lea. Before we generated: _test: ## @test movq _G@GOTPCREL(%rip), %rax leaq (%rax), %rax ret now we produce: _test: ## @test movq _G@GOTPCREL(%rip), %rax ret This is part of rdar://9289558 llvm-svn: 129662
* Fix rdar://9289512 - not folding load into compare at -O0Chris Lattner2011-04-171-15/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | The basic issue here is that bottom-up isel is matching the branch and compare, and was failing to fold the load into the branch/compare combo. Fixing this (by allowing folding into any instruction of a sequence that is selected) allows us to produce things like: cmpb $0, 52(%rax) je LBB4_2 instead of: movb 52(%rax), %cl cmpb $0, %cl je LBB4_2 This makes the generated -O0 code run a bit faster, but also speeds up compile time by putting less pressure on the register allocator and generating less code. This was one of the biggest classes of missing load folding. Implementing this shrinks 176.gcc's c-decl.s (as a random example) by about 4% in (verbose-asm) line count. llvm-svn: 129656
* split a complex predicate out to a helper function. Simplify two for loops,Chris Lattner2011-04-171-10/+16
| | | | | | | which don't need to check for falling off the end of a block *and* end of phi nodes, since terminators are never phis. llvm-svn: 129655
* fix rdar://9289583 - fast isel should handle non-canonical commutative binopsChris Lattner2011-04-171-4/+23
| | | | | | | | | | allowing us to fold the immediate into the 'and' in this case: int test1(int i) { return 8&i; } llvm-svn: 129653
* PR9055: extend the fix to PR4050 (r70179) to apply to zext and anyext.Eli Friedman2011-04-161-2/+2
| | | | | | | Returning a new node makes the code try to replace the old node, which in the included testcase is killed by CSE. llvm-svn: 129650
* Unbreak the MSVC 2010 build.Francois Pichet2011-04-161-1/+2
| | | | | | For further information on this particular issue see: http://connect.microsoft.com/VisualStudio/feedback/details/520043/error-converting-from-null-to-a-pointer-type-in-std-pair llvm-svn: 129642
* Remove unused variable.Benjamin Kramer2011-04-161-5/+2
| | | | llvm-svn: 129639
* Put each personality function in a section. This fixes the gnu ld warning:Rafael Espindola2011-04-162-8/+36
| | | | | | error in foo.o; no .eh_frame_hdr table will be created. llvm-svn: 129635
* Fix divmod libcall lowering. Convert to {S|U}DIVREM first and then expand ↵Evan Cheng2011-04-161-71/+65
| | | | | | the node to a libcall. rdar://9280991 llvm-svn: 129633
* Introduce support to encode Objective-C property information in debugging ↵Devang Patel2011-04-161-0/+31
| | | | | | information generated for an interface. llvm-svn: 129624
* Some refactoring suggested by Anton Korobeynikov.Rafael Espindola2011-04-152-41/+29
| | | | llvm-svn: 129600
* Teach the SplitKit blitter to handle multiply defined values as well.Jakob Stoklund Olesen2011-04-152-96/+223
| | | | | | | | | | | | | | The transferValues() function can now handle both singly and multiply defined values, as long as the resulting live range is known. Only rematerialized values have their live range recomputed by extendRange(). The updateSSA() function can now insert PHI values in bulk across multiple values in multiple target registers in one pass. The list of blocks received from transferValues() is in layout order which seems to work well for the iterative algorithm. Blocks from extendRange() are still in reverse BFS order, but this function is used so rarely now that it doesn't matter. llvm-svn: 129580
* Remember to set flag.Jakob Stoklund Olesen2011-04-151-0/+1
| | | | llvm-svn: 129579
* Add 129518 back with a fix for when we are producing eh just because of ↵Rafael Espindola2011-04-152-16/+71
| | | | | | | | | debug info. Change ELF systems to use CFI for producing the EH tables. This reduces the size of the clang binary in Debug builds from 690MB to 679MB. llvm-svn: 129571
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-1522-32/+31
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* Revert r129518, "Change ELF systems to use CFI for producing the EH tables. ↵NAKAMURA Takumi2011-04-152-70/+15
| | | | | | | | This reduces the" It broke several builds. llvm-svn: 129557
* Fix another instance of the DAG combiner not using the correct type for the ↵Owen Anderson2011-04-141-3/+5
| | | | | | RHS of a shift. llvm-svn: 129522
* Change ELF systems to use CFI for producing the EH tables. This reduces theRafael Espindola2011-04-142-15/+70
| | | | | | size of the clang binary in Debug builds from 690MB to 679MB. llvm-svn: 129518
* In the pre-RA scheduler, maintain cmp+br proximity.Andrew Trick2011-04-142-13/+61
| | | | | | | | | | | | | | | | | | | | | | | | This is done by pushing physical register definitions close to their use, which happens to handle flag definitions if they're not glued to the branch. This seems to be generally a good thing though, so I didn't need to add a target hook yet. The primary motivation is to generate code closer to what people expect and rule out missed opportunity from enabling macro-op fusion. As a side benefit, we get several 2-5% gains on x86 benchmarks. There is one regression: SingleSource/Benchmarks/Shootout/lists slows down be -10%. But this is an independent scheduler bug that will be tracked separately. See rdar://problem/9283108. Incidentally, pre-RA scheduling is only half the solution. Fixing the later passes is tracked by: <rdar://problem/8932804> [pre-RA-sched] on x86, attempt to schedule CMP/TEST adjacent with condition jump Fixes: <rdar://problem/9262453> Scheduler unnecessary break of cmp/jump fusion llvm-svn: 129508
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