| Commit message (Collapse) | Author | Age | Files | Lines |
| |
|
|
|
|
|
|
| |
instead of init'ing it maximally to zeros on entry. getFreePhysReg
is pretty hot and only a few elements are typically used. This speeds
up linscan by 5% on 176.gcc.
llvm-svn: 47631
|
| |
|
|
| |
llvm-svn: 47629
|
| |
|
|
|
|
| |
would have been a Godsend here!
llvm-svn: 47625
|
| |
|
|
| |
llvm-svn: 47623
|
| |
|
|
| |
llvm-svn: 47612
|
| |
|
|
|
|
| |
also fixes cfrac, flops, and 175.vpr
llvm-svn: 47605
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
CodeGen/PowerPC/illegal-element-type.ll): suppose
a node X is processed, and processing maps it to
a node Y. Then X continues to exist in the DAG,
but with no users. While processing some other
node, a new node may be created that happens to
be equal to X, and thus X will be reused rather
than a truly new node. This can cause X to
"magically reappear", and since it is in the
Processed state in will not be reprocessed, so
at the end of type legalization the illegal node
X can still be present. The solution is to replace
X with Y whenever X gets resurrected like this.
llvm-svn: 47601
|
| |
|
|
| |
llvm-svn: 47598
|
| |
|
|
|
|
|
|
|
| |
vr1 = extract_subreg vr2, 3
...
vr3 = extract_subreg vr1, 2
The end result is vr3 is equal to vr2 with subidx 2.
llvm-svn: 47592
|
| |
|
|
|
|
|
|
|
| |
after legalize. Just because a constant is legal (e.g. 0.0 in SSE)
doesn't mean that its negated value is legal (-0.0). We could make
this stronger by checking to see if the negated constant is actually
legal post negation, but it doesn't seem like a big deal.
llvm-svn: 47591
|
| |
|
|
| |
llvm-svn: 47587
|
| |
|
|
| |
llvm-svn: 47566
|
| |
|
|
|
|
| |
a SignBitIsZero function to simplify a common use case.
llvm-svn: 47561
|
| |
|
|
|
|
| |
loads. This change doesn't really have any impact on codegen.
llvm-svn: 47557
|
| |
|
|
|
|
| |
result and operand types are legal.
llvm-svn: 47546
|
| |
|
|
| |
llvm-svn: 47545
|
| |
|
|
|
|
|
|
|
| |
out of illegal elements (BUILD_VECTOR). Uses and beefs
up BUILD_PAIR, though it didn't really have to. Like
most of LegalizeTypes, does not support soft-float.
This cures all "make check" vector building failures.
llvm-svn: 47537
|
| |
|
|
|
|
|
|
|
| |
%r3 on PPC) in their ASM files. However, it's hard for humans to read
during debugging. Adding a new field to the register data that lets you
specify a different name to be printed than the one that goes into the
ASM file -- %x3 instead of %r3, for instance.
llvm-svn: 47534
|
| |
|
|
|
|
| |
fixed stack slots.
llvm-svn: 47529
|
| |
|
|
|
|
| |
is avaliable at all uses regardless of whether it would be folded.
llvm-svn: 47526
|
| |
|
|
|
|
| |
isReallyTriviallyReMaterializable() returns true it doesn't confuse it as a "normal" re-materializable instruction.
llvm-svn: 47520
|
| |
|
|
| |
llvm-svn: 47507
|
| |
|
|
| |
llvm-svn: 47500
|
| |
|
|
|
|
|
|
| |
ESI, EDI, and EBP because of a bug in RALocal::isPhysRegAvailable(). For example, when
it checks if ESI is available, it then looks at registers aliases to ESI. SIL is marked -2 (not allocatable) but isPhysRegAvailable() incorrectly assumes it is in use and returns false for ESI.
llvm-svn: 47499
|
| |
|
|
| |
llvm-svn: 47496
|
| |
|
|
| |
llvm-svn: 47492
|
| |
|
|
|
|
| |
the way through. It is now used for codegen.
llvm-svn: 47484
|
| |
|
|
|
|
|
|
| |
operands if
the definition of the operand also reaches its uses.
llvm-svn: 47475
|
| |
|
|
| |
llvm-svn: 47468
|
| |
|
|
|
|
|
| |
that a value is >= 32, check that all of the high bits are zero, not
just one or more.
llvm-svn: 47467
|
| |
|
|
|
|
|
| |
early clobbers if the clobber list contains a *register* not some thing
like {memory}, {dirflag} etc.
llvm-svn: 47457
|
| |
|
|
|
|
|
|
|
| |
any, we force sdisel to do all regalloc for an asm. This
leads to gross but correct codegen.
This fixes the rest of PR2078.
llvm-svn: 47454
|
| |
|
|
| |
llvm-svn: 47453
|
| |
|
|
| |
llvm-svn: 47452
|
| |
|
|
| |
llvm-svn: 47448
|
| |
|
|
| |
llvm-svn: 47435
|
| |
|
|
|
|
| |
failing on archs that haven't implemented them yet
llvm-svn: 47430
|
| |
|
|
|
|
| |
Eli Friedman. This implements CodeGen/Generic/2008-02-20-MatchingMem.ll.
llvm-svn: 47428
|
| |
|
|
|
|
|
|
|
|
| |
inline asms.
Fix PR2078 by marking aliases of registers used when a register is
marked used. This prevents EAX from being allocated when AX is listed
in the clobber set for the asm.
llvm-svn: 47426
|
| |
|
|
| |
llvm-svn: 47416
|
| |
|
|
|
|
|
|
| |
No need to go up more levels. A def of a register also sets its sub-registers
(so if PhysRegInfo[SuperReg] is NULL, it means SuperReg's super registers are
not previously defined).
llvm-svn: 47399
|
| |
|
|
| |
llvm-svn: 47395
|
| |
|
|
| |
llvm-svn: 47389
|
| |
|
|
| |
llvm-svn: 47388
|
| |
|
|
|
|
|
|
|
| |
and splitting extract_subvector. This fixes nine
"make check" testcases, for example
2008-02-04-ExtractSubvector.ll and (partially)
CodeGen/Generic/vector.ll.
llvm-svn: 47384
|
| |
|
|
| |
llvm-svn: 47383
|
| |
|
|
| |
llvm-svn: 47382
|
| |
|
|
| |
llvm-svn: 47381
|
| |
|
|
| |
llvm-svn: 47380
|
| |
|
|
| |
llvm-svn: 47375
|