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* Add EnableIPRA to TargetOptions, and move the cl::opt -enable-ipra to ↵Mehdi Amini2016-07-132-8/+4
| | | | | | | | | | | | TargetMachine.cpp Avoid exposing a cl::opt in a public header and instead promote this option in the API. Alternatively, we could land the cl::opt in CommandFlags.h so that it is available to every tool, but we would still have to find an option for clang. llvm-svn: 275348
* [IPRA] Set callee saved registers to none for local function when IPRA is ↵Mehdi Amini2016-07-133-10/+29
| | | | | | | | | | | | | | | | | | | | enabled. IPRA try to optimize caller saved register by propagating register usage information from callee to caller so it is beneficial to have caller saved registers compare to callee saved registers when IPRA is enabled. Please find more detailed explanation here https://groups.google.com/d/msg/llvm-dev/XRzGhJ9wtZg/tjAJqb0eEgAJ. This change makes local function do not have any callee preserved register when IPRA is enabled. A simple test case is also added to verify this change. Patch by Vivek Pandya <vivekvpandya@gmail.com> Differential Revision: http://reviews.llvm.org/D21561 llvm-svn: 275347
* Fix copy/paste bug in r275340.Michael Kuperstein2016-07-131-1/+1
| | | | llvm-svn: 275343
* MIRParser: Move SlotMapping and SourceMgr refs to PFS; NFCMatthias Braun2016-07-133-88/+69
| | | | | | | | Code cleanup: Move references to SlotMapping and SourceMgr into the PerFunctionMIParsingState to avoid unnecessary passing around in parameters. llvm-svn: 275342
* [DAG] Correctly chain masked loadsMichael Kuperstein2016-07-131-9/+8
| | | | | | | | | If a masked loads is not added to the chain, it should not reset the chain's root. This fixes the remaining part of PR28515. llvm-svn: 275340
* [MI] Clean up some loops over MachineInstr::memoperands(). NFCJustin Lebar2016-07-131-14/+11
| | | | | | | Use range-based for loops and llvm::any_of instead of explicit iterators. llvm-svn: 275332
* [MI] Fix MachineInstr::isInvariantLoad.Justin Lebar2016-07-131-2/+1
| | | | | | | | | | | | | | | | | | | | Summary: Previously it would say we had an invariant load if any of the memory operands were invariant. But the load should be invariant only if *all* the memory operands are invariant. No testcase because this has proven to be very difficult to tickle in practice. As just one example, ARM's ldrd instruction, which loads 64 bits into two 32-bit regs, is theoretically affected by this. But when it's produced, it loses its memoperands' invariance bits! Reviewers: jfb Subscribers: llvm-commits, aemerson Differential Revision: http://reviews.llvm.org/D22318 llvm-svn: 275331
* MIRParser: Move MachineFunction reference into PFS; NFCMatthias Braun2016-07-133-141/+132
| | | | | | | | | | Code cleanup: The PerFunctionMIParsingState is per function, moving a reference into PFS we can avoid passing around the MachineFunction in an extra parameter most of the time. Also change most signatures to consistently pass PFS reference first. llvm-svn: 275329
* [MIR] Print on the given output instead of stderr.Quentin Colombet2016-07-131-1/+1
| | | | | | | | | | | | Currently the MIR framework prints all its outputs (errors and actual representation) on stderr. This patch fixes that by printing the regular output in the output specified with -o. Differential Revision: http://reviews.llvm.org/D22251 llvm-svn: 275314
* Reverting r275284 due to platform-specific test failuresAndrew Kaylor2016-07-132-47/+0
| | | | llvm-svn: 275304
* Fix for Bug 26903, adds support to inline __builtin_mempcpyAndrew Kaylor2016-07-132-0/+47
| | | | | | | | Patch by Sunita Marathe Differential Revision: http://reviews.llvm.org/D21920 llvm-svn: 275284
* PatchableFunction: Skip pseudos that do not create codeMatthias Braun2016-07-131-5/+23
| | | | | | This fixes http://llvm.org/PR28524 llvm-svn: 275278
* GlobalISel: freeze reserved regs after IRTranslator.Tim Northover2016-07-121-0/+5
| | | | | | | | | | We can freeze the registers after the MachineFrameInfo has been configured (by telling it about calls, inline asm, ...). This doesn't happen at all yet, but will be part of IR translation. Fixes -verify-machineinstrs assertion. llvm-svn: 275221
* BranchFolding: Use LivePhysReg to update live in lists.Matthias Braun2016-07-122-29/+30
| | | | | | | | | | | | | | | Use LivePhysRegs with a backwards walking algorithm to update live in lists, this way the results do not depend on the presence of kill flags anymore. This patch also reduces the number of registers added as live-in. Previously all pristine registers as well as all sub registers of a super register were added resulting in unnecessarily large live in lists. This fixed https://llvm.org/PR25263. Differential Revision: http://reviews.llvm.org/D22027 llvm-svn: 275201
* Fix printing of debugging information in LiveIntervals::shrinkToUsesKrzysztof Parzyszek2016-07-121-1/+1
| | | | | | | Print VNI->def before calling VNI->markUnused(), since markUnused makes the def invalid. llvm-svn: 275196
* Add print/dump routines to LiveInterval::SubRangeKrzysztof Parzyszek2016-07-121-10/+18
| | | | llvm-svn: 275194
* [codeview] Improved array type support.Amjad Aboud2016-07-124-33/+87
| | | | | | | | | | | | Added support for: 1. Multi dimension array. 2. Array of structure type, which previously was declared incompletely. 3. Dynamic size array. 4. Array where element type is a typedef, volatile or constant (this should resolve PR28311). Differential Revision: http://reviews.llvm.org/D21526 llvm-svn: 275167
* Codegen: Fix comment in BranchFolding.cppKyle Butt2016-07-111-7/+6
| | | | | | | | Blocks to be tail-merged may share more than one successor. Correct the comment to state that they share a specific successor, SuccBB, rather than a single successor, which is not true. llvm-svn: 275104
* fix documentation comments; NFCSanjay Patel2016-07-111-42/+7
| | | | llvm-svn: 275101
* [IPRA] Properly compute register usage at call sites.Chad Rosier2016-07-112-4/+6
| | | | | | | | Differential Revision: http://reviews.llvm.org/D21395 Patch by Vivek Pandya. PR28144 llvm-svn: 275087
* Provide support for preserving assembly commentsNirav Dave2016-07-111-0/+2
| | | | | | | | | | | | | | | | | Preserve assembly comments from input in output assembly and flags to toggle property. This is on by default for inline assembly and off in llvm-mc. Parsed comments are emitted immediately before an EOL which generally places them on the expected line. Reviewers: rtrieu, dwmw2, rnk, majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D20020 llvm-svn: 275058
* [DAG] make isConstantSplatVector() available to the rest of loweringSanjay Patel2016-07-102-32/+25
| | | | llvm-svn: 275025
* fix documentation comments; NFCSanjay Patel2016-07-101-11/+3
| | | | llvm-svn: 275021
* reformat, fix comments/names; NFCISanjay Patel2016-07-101-27/+22
| | | | llvm-svn: 275015
* Give helper classes/functions internal linkage. NFC.Benjamin Kramer2016-07-101-1/+1
| | | | llvm-svn: 275014
* [COFF, Dwarf] Don't emit DW_AT_location for dllimported entitiesDavid Majnemer2016-07-092-55/+66
| | | | | | | There exists no relocation which can describe the address of a dllimported variable: do not try to describe their location. llvm-svn: 274986
* fix documentation comments; NFCSanjay Patel2016-07-093-159/+143
| | | | llvm-svn: 274981
* LivePhysRegs: addLiveOuts() can skip addPristines() in ret blockMatthias Braun2016-07-091-1/+2
| | | | | | | | Drive-by improvement: We would 1) add CSRs, 2) remove callee saved CSRs and 3) add all CSRs again for the return block. Just adding CSRs once obviously gives the same results. llvm-svn: 274955
* VirtRegMap: Replace some identity copies with KILL instructions.Matthias Braun2016-07-091-9/+27
| | | | | | | | | | | | | | An identity COPY like this: %AL = COPY %AL, %EAX<imp-def> has no semantic effect, but encodes liveness information: Further users of %EAX only depend on this instruction even though it does not define the full register. Replace the COPY with a KILL instruction in those cases to maintain this liveness information. (This reverts a small part of r238588 but this time adds a comment explaining why a KILL instruction is useful). llvm-svn: 274952
* AsmPrinter: Fix emitKill() not flush()ing a raw_string_ostreamMatthias Braun2016-07-091-1/+1
| | | | llvm-svn: 274951
* Reapply r274829 with fix for FP vectorsMatt Arsenault2016-07-081-2/+4
| | | | llvm-svn: 274937
* Allow dead insts to be kept in DeadRemat only when they are rematerializable.Wei Mi2016-07-085-18/+27
| | | | | | | | | | | | | | | Because isReallyTriviallyReMaterializableGeneric puts many limits on rematerializable instructions, this fix can prevent instructions with tied virtual operands and instructions with virtual register uses from being kept in DeadRemat, so as to workaround the live interval consistency problem for the dummy instructions kept in DeadRemat. But we still need to fix the live interval consistency problem. This patch is just a short time relieve. PR28464 has been filed as a reminder. Differential Revision: http://reviews.llvm.org/D19486 llvm-svn: 274928
* Revert r274829, it caused PR28472.Nico Weber2016-07-081-1/+1
| | | | llvm-svn: 274916
* AsmPrinter: Avoid implicit iterator conversions in ↵Duncan P. N. Exon Smith2016-07-081-2/+2
| | | | | | DbgValueHistoryCalculator, NFC llvm-svn: 274911
* SelectionDAG: Avoid implicit iterator conversions in SelectionDAGBuilder, NFCDuncan P. N. Exon Smith2016-07-081-1/+2
| | | | llvm-svn: 274907
* SelectionDAG: Avoid implicit iterator conversions in SelectionDAGISel, NFCDuncan P. N. Exon Smith2016-07-081-8/+8
| | | | llvm-svn: 274904
* SelectionDAG: Avoid implicit iterator conversions in ScheduleDAGSDNodes, NFCDuncan P. N. Exon Smith2016-07-081-1/+1
| | | | llvm-svn: 274903
* SelectionDAG: Avoid implicit iterator conversions in FastISel, NFCDuncan P. N. Exon Smith2016-07-081-3/+4
| | | | llvm-svn: 274899
* CodeGen: Avoid iterator conversions in TwoAddressInstructionPass, NFCDuncan P. N. Exon Smith2016-07-081-55/+51
| | | | | | | | | | | | Mostly through preferring MachineInstr&, avoid implicit conversions from iterator to pointer. Although this may bitrot (since there are other uses blocking me from removing the implicit operator), this removes the last of the implicit conversions from MachineInstrBundleIterator to MachineInstr* in the LLVMCodeGen build target. llvm-svn: 274893
* CodeGen: Use MachineInstr& in StackSlotColoring, NFCDuncan P. N. Exon Smith2016-07-081-14/+11
| | | | | | Avoid implicit iterator to pointer conversions. llvm-svn: 274892
* CodeGen: Use MachineInstr& in RegisterScavenging, NFCDuncan P. N. Exon Smith2016-07-081-16/+15
| | | | | | | Prefer MachineInstr& in order to avoid implicit conversions from MachineInstrBundleIterator to MachineInstr*. llvm-svn: 274888
* [CodeGen, TargetPassConfig] Remove a race from createRegAllocPassDavid Majnemer2016-07-081-6/+14
| | | | | | | | The createRegAllocPass reads and writes to a global variable 'Registry' via calls to getDefault and setDefault. Run this under a call_once to avoid races. llvm-svn: 274875
* PeepholeOptimizer: Make pass name match DEBUG_TYPEMatt Arsenault2016-07-081-2/+2
| | | | llvm-svn: 274874
* Do not expand SDIV when compiling for minimum code sizeSjoerd Meijer2016-07-081-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D22139 llvm-svn: 274855
* Addressing post-commit comments regarding not expanding UDIV;Sjoerd Meijer2016-07-081-2/+2
| | | | | | we don't expand only when compiling for minimum code size. llvm-svn: 274847
* Code size optimisation: don't expand a div to a mul and and a shift sequence.Sjoerd Meijer2016-07-081-0/+5
| | | | | | | | | As a result, the urem instruction will not be expanded to a sequence of umull, lsrs, muls and sub instructions, but just a call to __aeabi_uidivmod. Differential Revision: http://reviews.llvm.org/D22131 llvm-svn: 274843
* Bug 28444: Fix assertion when extract_vector_elt has mismatched typeMatt Arsenault2016-07-081-1/+1
| | | | | | | For some reason extract_vector_elt is sometimes allowed to have a different result type than the vector element type. llvm-svn: 274829
* [PM] Port UnreachableBlockElim to the new Pass ManagerWei Mi2016-07-082-25/+39
| | | | | | Differential Revision: http://reviews.llvm.org/D22124 llvm-svn: 274824
* Include SelectionDAGISel in the opt-bisect processAndrew Kaylor2016-07-071-1/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D21143 llvm-svn: 274786
* [CodeView] Implement support for thread-local variablesDavid Majnemer2016-07-071-4/+15
| | | | llvm-svn: 274734
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