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* Adjust the scavenge register spilling to allow the target to choose anJim Grosbach2009-10-191-3/+2
| | | | | | | | | | appropriate restore location for the spill as well as perform the actual save and restore. The Thumb1 target uses this to make sure R12 is not clobbered while a spilled scavenger register is live there. llvm-svn: 84554
* Revert r84295, this unbreaks llvm-gcc bootstrap on x86-64/linuxAnton Korobeynikov2009-10-191-355/+177
| | | | llvm-svn: 84516
* Fix a typo in a comment.Dan Gohman2009-10-191-1/+1
| | | | llvm-svn: 84504
* Change a few instance variables to be local variables.Dan Gohman2009-10-191-11/+6
| | | | llvm-svn: 84503
* Spill slots cannot alias.Evan Cheng2009-10-183-9/+16
| | | | llvm-svn: 84432
* -Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixedEvan Cheng2009-10-189-67/+73
| | | | | | | | | | | stack slots and giving them different PseudoSourceValue's did not fix the problem of post-alloc scheduling miscompiling llvm itself. - Apply Dan's conservative workaround by assuming any non fixed stack slots can alias other memory locations. This means a load from spill slot #1 cannot move above a store of spill slot #2. - Enable post-alloc scheduling for x86 at optimization leverl Default and above. llvm-svn: 84424
* Only fixed stack objects and spill slots should be get FixedStack ↵Evan Cheng2009-10-187-42/+64
| | | | | | PseudoSourceValue. llvm-svn: 84411
* Fix my -Asserts warning fix.Daniel Dunbar2009-10-171-2/+3
| | | | llvm-svn: 84372
* Suppress -Asserts warning.Daniel Dunbar2009-10-171-2/+2
| | | | llvm-svn: 84327
* Distinquish stack slots from other stack objects. They (and fixed objects) ↵Evan Cheng2009-10-174-5/+5
| | | | | | get FixedStack PseudoSourceValues. llvm-svn: 84326
* Revert 84315 for now. Re-thinking the patch.Evan Cheng2009-10-178-29/+26
| | | | llvm-svn: 84321
* Rename getFixedStack to getStackObject. The stack objects represented are notEvan Cheng2009-10-178-26/+29
| | | | | | necessarily fixed. Only those will negative frame indices are "fixed." llvm-svn: 84315
* 80 col violation.Evan Cheng2009-10-171-1/+2
| | | | llvm-svn: 84311
* Delete an obsolete comment.Dan Gohman2009-10-171-2/+1
| | | | llvm-svn: 84300
* Remove MallocInst from LLVM Instructions.Victor Hernandez2009-10-172-44/+0
| | | | llvm-svn: 84299
* Enhance CodePlacementOpt's unconditional intra-loop branch elimination logicDan Gohman2009-10-171-177/+354
| | | | | | | | | | | | to be more general and understand more varieties of loops. Teach CodePlacementOpt to reorganize the basic blocks of a loop so that they are contiguous. This also includes a fair amount of logic for preserving fall-through edges while doing so. This fixes a BranchFolding-ism where blocks which can't be made to use a fall-through edge and don't conveniently fit anywhere nearby get tossed out to the end of the function. llvm-svn: 84295
* Allow widening of extract subvectorMon P Wang2009-10-162-0/+8
| | | | llvm-svn: 84279
* Do not emit name entry for a pointer type.Devang Patel2009-10-161-1/+1
| | | | llvm-svn: 84276
* Change createPostRAScheduler so it can be turned off at llc -O1.Evan Cheng2009-10-162-5/+7
| | | | llvm-svn: 84273
* If there is not any llvm instruction associated with each lexical scope ↵Devang Patel2009-10-161-2/+10
| | | | | | encoded in debug info then create such scope on demand for variable info. llvm-svn: 84262
* If post-alloc scheduler is not enabled, it should return false, not true.Evan Cheng2009-10-161-3/+3
| | | | llvm-svn: 84248
* Indent code.Zhongxing Xu2009-10-161-1/+1
| | | | llvm-svn: 84247
* 80 column violation.Evan Cheng2009-10-161-1/+2
| | | | llvm-svn: 84244
* Report errors correctly for unselected target intrinsics.Jakob Stoklund Olesen2009-10-151-6/+9
| | | | llvm-svn: 84193
* Make CodePlacementOpt align loops, rather than loop headers. TheDan Gohman2009-10-151-71/+30
| | | | | | | | | | header is just the entry block to the loop, and it needn't be at the top of the loop in the code layout. Remove the code that suppressed loop alignment for outer loops, so that outer loops are aligned. llvm-svn: 84158
* When LiveVariables is adding implicit-def to model "partial dead", add the ↵Evan Cheng2009-10-141-1/+12
| | | | | | earlyclobber marker if the superreg def has it. llvm-svn: 84153
* Print earlyclobber for implicit-defs as well.Evan Cheng2009-10-141-6/+6
| | | | llvm-svn: 84152
* Make loop not recalc getNumOperands() each time aroundJim Grosbach2009-10-141-3/+2
| | | | llvm-svn: 84138
* Add support to record DbgScope as inlined scope.Devang Patel2009-10-142-25/+44
| | | | llvm-svn: 84134
* quiet compiler warningJim Grosbach2009-10-141-1/+1
| | | | llvm-svn: 84133
* I don't see any point in having both eh.selector.i32 and eh.selector.i64,Duncan Sands2009-10-144-29/+27
| | | | | | | | | | | | | so get rid of eh.selector.i64 and rename eh.selector.i32 to eh.selector. Likewise for eh.typeid.for. This aligns us with gcc, which always uses a 32 bit value for the selector on all platforms. My understanding is that the register allocator used to assert if the selector intrinsic size didn't match the pointer size, and this was the reason for introducing the two variants. However my testing shows that this is no longer the case (I fixed some bugs in selector lowering yesterday, and some more today in the fastisel path; these might have caused the original problems). llvm-svn: 84106
* This remat entry is basically done. There are hooks to allow targetsDan Gohman2009-10-141-38/+0
| | | | | | | | to remat non-load instructions as loads, and the remat code now uses the UnmodeledSideEffects flags, MachineMemOperands, and similar things to decide which instructions are valid for rematerialization. llvm-svn: 84060
* Add a few README.txt items.Dan Gohman2009-10-131-0/+29
| | | | llvm-svn: 84059
* s/DebugLoc.CompileUnit/DebugLoc.Scope/gDevang Patel2009-10-135-22/+23
| | | | | | s/DebugLoc.InlinedLoc/DebugLoc.InlinedAtLoc/g llvm-svn: 84054
* Introduce new convenience methods for sign extending orDuncan Sands2009-10-132-54/+22
| | | | | | | | | | | | truncating an SDValue (depending on whether the target type is bigger or smaller than the value's type); or zero extending or truncating it. Use it in a few places (this seems to be a popular operation, but I only modified cases of it in SelectionDAGBuild). In particular, the eh_selector lowering was doing this wrong due to a repeated rather than inverted test, fixed with this change. llvm-svn: 84027
* Add debugging output.David Goodwin2009-10-131-2/+12
| | | | llvm-svn: 84011
* Fix a -Asserts warning.Daniel Dunbar2009-10-131-2/+3
| | | | llvm-svn: 83950
* Find enclosing subprogram info.Devang Patel2009-10-121-1/+19
| | | | llvm-svn: 83922
* Set default location for a function if it is not set.Devang Patel2009-10-121-0/+2
| | | | llvm-svn: 83921
* Revert the kludge in 76703. I got a cleanDale Johannesen2009-10-122-23/+25
| | | | | | | | | bootstrap of FSF-style PPC, so there is some reason to believe the original bug (which was never analyzed) has been fixed, probably by 82266. llvm-svn: 83871
* Remove a redundant member variable.Dan Gohman2009-10-121-1/+0
| | | | llvm-svn: 83857
* More heuristics for Combiner-AA. Still catches all important cases, butNate Begeman2009-10-121-6/+19
| | | | | | | compile time penalty on gnugo, the worst case in MultiSource, is down to about 2.5% from 30% llvm-svn: 83824
* Fix PR5087, patch by Jakub Staszak!Chris Lattner2009-10-121-0/+1
| | | | llvm-svn: 83822
* Create a new InstrEmitter class for translating SelectionDAG nodesDan Gohman2009-10-105-183/+263
| | | | | | | | into MachineInstrs. This is mostly just moving the code from ScheduleDAGSDNodesEmit.cpp into a new class. This decouples MachineInstr emitting from scheduling. llvm-svn: 83699
* Make getMachineNode return a MachineSDNode* instead of a generic SDNode*Dan Gohman2009-10-101-42/+53
| | | | | | | since it won't do any folding. This will help avoid some inconvenient casting. llvm-svn: 83698
* Fix a missing initialization of PostRAScheduler's AA member.Dan Gohman2009-10-101-0/+2
| | | | llvm-svn: 83695
* The ScheduleDAG framework now requires an AliasAnalysis argument, thoughDan Gohman2009-10-095-5/+5
| | | | | | it isn't needed in the ScheduleDAGSDNodes schedulers. llvm-svn: 83691
* Factor out LiveIntervalAnalysis' code to determine whether an instructionDan Gohman2009-10-0912-116/+135
| | | | | | | | | | | | | | is trivially rematerializable and integrate it into TargetInstrInfo::isTriviallyReMaterializable. This way, all places that need to know whether an instruction is rematerializable will get the same answer. This enables the useful parts of the aggressive-remat option by default -- using AliasAnalysis to determine whether a memory location is invariant, and removes the questionable parts -- rematting operations with virtual register inputs that may not be live everywhere. llvm-svn: 83687
* Extract scope information from the variable itself, instead of relying on ↵Devang Patel2009-10-094-32/+41
| | | | | | | | alloca or llvm.dbg.declare location. While recording beginning of a function, use scope info from the first location entry instead of just relying on first location entry itself. llvm-svn: 83684
* isTriviallyReMaterializable checks theDan Gohman2009-10-094-7/+4
| | | | | | | TargetInstrDesc::isRematerializable flag, so it isn't necessary to do this check in its callers. llvm-svn: 83671
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