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* Skip unused values.Jakob Stoklund Olesen2011-02-041-1/+3
| | | | llvm-svn: 124842
* Also compute interference intervals for blocks with no uses.Jakob Stoklund Olesen2011-02-041-3/+1
| | | | | | | | When the live range is live through a block that doesn't use the register, but that has interference, region splitting wants to split at the top and bottom of the basic block. llvm-svn: 124839
* Verify kill flags conservatively.Jakob Stoklund Olesen2011-02-041-18/+5
| | | | | | | | | | Allow a live range to end with a kill flag, but don't allow a kill flag that doesn't end the live range. This makes the machine code verifier more useful during register allocation when kill flag computation is deferred. llvm-svn: 124838
* whitespaceAndrew Trick2011-02-031-18/+18
| | | | llvm-svn: 124827
* Ensure that the computed interference intervals actually overlap their basic ↵Jakob Stoklund Olesen2011-02-031-3/+12
| | | | | | blocks. llvm-svn: 124815
* Tweak debug output from SlotIndexes.Jakob Stoklund Olesen2011-02-031-1/+5
| | | | llvm-svn: 124814
* Add debug output and asserts to the phi-connecting code.Jakob Stoklund Olesen2011-02-031-2/+13
| | | | llvm-svn: 124813
* Fix coloring bug when mapping values in the middle of a live-through block.Jakob Stoklund Olesen2011-02-031-7/+7
| | | | | | | | | | If the found value is not live-through the block, we should only add liveness up to the requested slot index. When the value is live-through, the whole block should be colored. Bug found by SSA verification in the machine code verifier. llvm-svn: 124812
* Return live range end points from SplitEditor::enter*/leave*.Jakob Stoklund Olesen2011-02-033-62/+48
| | | | | | | These end points come from the inserted copies, and can be passed directly to useIntv. This simplifies the coloring code. llvm-svn: 124799
* Silence an MSVC warningJakob Stoklund Olesen2011-02-031-1/+1
| | | | llvm-svn: 124798
* Reapply this.Eric Christopher2011-02-034-224/+181
| | | | llvm-svn: 124779
* Temporarily revert 124765 in an attempt to find the cycle breaking bootstrap.Eric Christopher2011-02-034-181/+224
| | | | llvm-svn: 124778
* Defer SplitKit value mapping until all defs are available.Jakob Stoklund Olesen2011-02-034-224/+181
| | | | | | | | | | | | | | | | | | | The greedy register allocator revealed some problems with the value mapping in SplitKit. We would sometimes start mapping values before all defs were known, and that could change a value from a simple 1-1 mapping to a multi-def mapping that requires ssa update. The new approach collects all defs and register assignments first without filling in any live intervals. Only when finish() is called, do we compute liveness and mapped values. At this time we know with certainty which values map to multiple values in a split range. This also has the advantage that we can compute live ranges based on the remaining uses after rematerializing at split points. The current implementation has many opportunities for compile time optimization. llvm-svn: 124765
* Add support to describe template value parameter in debug info.Devang Patel2011-02-022-0/+25
| | | | llvm-svn: 124755
* Add support to describe template parameter type in debug info.Devang Patel2011-02-022-0/+32
| | | | llvm-svn: 124752
* Given a pair of floating point load and store, if there are no other uses ofEvan Cheng2011-02-021-0/+65
| | | | | | | | | | | | | | | | | | | the load, then it may be legal to transform the load and store to integer load and store of the same width. This is done if the target specified the transformation as profitable. e.g. On arm, this can transform: vldr.32 s0, [] vstr.32 s0, [] to ldr r12, [] str r12, [] rdar://8944252 llvm-svn: 124708
* Take Bill Wendling's suggestion for structuring a couple of asserts.Matt Beaumont-Gay2011-02-011-6/+6
| | | | llvm-svn: 124688
* Keep track of incoming argument's location while emitting LiveIns.Devang Patel2011-01-314-4/+22
| | | | llvm-svn: 124611
* Fix bug where ReduceLoadWidth was creating illegal ZEXTLOAD instructions.Richard Osborne2011-01-311-2/+2
| | | | llvm-svn: 124587
* Clarify the LSDASection NULL checkAnton Korobeynikov2011-01-301-0/+2
| | | | llvm-svn: 124569
* Respect the -tail-dup-size command line option even when optimizing for size.Jakob Stoklund Olesen2011-01-301-1/+2
| | | | | | | This is similar to the -unroll-threshold option. There should be no change in behavior when -tail-dup-size is not explicit on the llc command line. llvm-svn: 124564
* Teach DAGCombine to fold fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, ↵Benjamin Kramer2011-01-301-0/+23
| | | | | | | | | | | | | | | | | | c1+c2) when c1 equals the amount of bits that are truncated off. This happens all the time when a smul is promoted to a larger type. On x86-64 we now compile "int test(int x) { return x/10; }" into movslq %edi, %rax imulq $1717986919, %rax, %rax movq %rax, %rcx shrq $63, %rcx sarq $34, %rax <- used to be "shrq $32, %rax; sarl $2, %eax" addl %ecx, %eax This fires 96 times in gcc.c on x86-64. llvm-svn: 124559
* Add the missing sub identity "A-(A-B) -> B" to DAGCombine.Benjamin Kramer2011-01-291-0/+3
| | | | | | | | This happens e.g. for code like "X - X%10" where we lower the modulo operation to a series of multiplies and shifts that are then subtracted from X, leading to this missed optimization. llvm-svn: 124532
* Re-apply r124518 with fix. Watch out for invalidated iterator.Evan Cheng2011-01-291-4/+7
| | | | llvm-svn: 124526
* Revert r124518. It broke Linux self-host.Evan Cheng2011-01-291-7/+4
| | | | llvm-svn: 124522
* Re-commit r124462 with fixes. Tail recursion elim will now dup ret into ↵Evan Cheng2011-01-291-4/+7
| | | | | | unconditional predecessor to enable TCE on demand. llvm-svn: 124518
* Revert r124462. There are a few big regressions that I need to fix first.Evan Cheng2011-01-281-7/+4
| | | | llvm-svn: 124478
* Fix build with stdcxx by using llvm::next. Patch by Joerg Sonnenberger!Nick Lewycky2011-01-281-1/+2
| | | | llvm-svn: 124472
* Print the visibility of declarations.Rafael Espindola2011-01-281-1/+14
| | | | llvm-svn: 124468
* - Stop simplifycfg from duplicating "ret" instructions into unconditionalEvan Cheng2011-01-281-4/+7
| | | | | | | | branches. PR8575, rdar://5134905, rdar://8911460. - Allow codegen tail duplication to dup small return blocks after register allocation is done. llvm-svn: 124462
* Remove a temporary workaround for a lencod miscompile. Depends on the fix in ↵Andrew Trick2011-01-271-2/+0
| | | | | | r124442. llvm-svn: 124443
* VirtRegRewriter fix: update kill flags, which are used by the scavenger.Andrew Trick2011-01-271-64/+88
| | | | | | | | | | | | | | | | | | | | | | | rdar://problem/8893967: JM/lencod miscompile at -arch armv7 -mthumb -O3 Added ResurrectKill to remove kill flags after we decide to reused a physical register. And (hopefully) ensure that we call it in all the right places. Sorry, I'm not checking in a unit test given that it's a miscompile I can't reproduce easily with a toy example. Failures in the rewriter depend on a series of heuristic decisions maked during one of the many upstream phases in codegen. This case would require coercing regalloc to generate a couple of rematerialzations in a way that causes the scavenger to reuse the same register at just the wrong point. The general way to test this is to implement kill flags verification. Then we could have a simple, robust compile-only unit test. That would be worth doing if the whole pass was not about to disappear. At this point we focus verification work on the next generation of regalloc. llvm-svn: 124442
* Speculatively revert r124380.Devang Patel2011-01-272-4/+1
| | | | llvm-svn: 124397
* While legalizing SDValues do not drop SDDbgValues, trasfer them to new legal ↵Devang Patel2011-01-272-1/+4
| | | | | | | | nodes. Take 2. This includes fix for dragonegg crash. llvm-svn: 124380
* Avoid modifying the OneClassForEachPhysReg map while iterating over it.Bob Wilson2011-01-271-2/+6
| | | | | | | | | Linear scan regalloc is currently assuming that any register aliased with a member of a regclass must also be in at least one regclass. That is not always true. For example, for X86, RIP is in a regclass but IP is not. If you're unlucky, this can cause a crash by invalidating the iterator. llvm-svn: 124365
* Try harder to not have unused variables.Matt Beaumont-Gay2011-01-271-0/+2
| | | | llvm-svn: 124350
* Opt-mode -Wunused-variable cleanupMatt Beaumont-Gay2011-01-271-4/+2
| | | | llvm-svn: 124346
* Reapply 124301Devang Patel2011-01-271-1/+5
| | | | llvm-svn: 124339
* Initialize variable to get rid of clang warning.Bill Wendling2011-01-261-1/+1
| | | | llvm-svn: 124331
* Revert 124301.Devang Patel2011-01-261-5/+1
| | | | llvm-svn: 124327
* Revert r124302Devang Patel2011-01-261-3/+0
| | | | llvm-svn: 124320
* [AVX] Add INSERT_SUBVECTOR and support it on x86. This provides aDavid Greene2011-01-262-0/+73
| | | | | | | | default implementation for x86, going through the stack in a similr fashion to how the codegen implements BUILD_VECTOR. Eventually this will get matched to VINSERTF128 if AVX is available. llvm-svn: 124307
* While legalizing SDValues do not drop SDDbgValues, trasfer them to new legal ↵Devang Patel2011-01-261-0/+3
| | | | | | nodes. llvm-svn: 124302
* Process valid SDDbgValues even if the node does not have any order assigned.Devang Patel2011-01-261-1/+5
| | | | llvm-svn: 124301
* Refactor.Devang Patel2011-01-261-19/+30
| | | | llvm-svn: 124300
* [AVX] Support EXTRACT_SUBVECTOR on x86. This provides a defaultDavid Greene2011-01-262-5/+24
| | | | | | | | implementation of EXTRACT_SUBVECTOR for x86, going through the stack in a similr fashion to how the codegen implements BUILD_VECTOR. Eventually this will get matched to VEXTRACTF128 if AVX is available. llvm-svn: 124292
* Rename member variables to follow the rest of LLVM.Jakob Stoklund Olesen2011-01-262-295/+295
| | | | | | No functional change. llvm-svn: 124257
* Provide an interface to transfer SDDbgValue from one SDNode to another.Devang Patel2011-01-252-0/+25
| | | | llvm-svn: 124245
* Resolve DanglingDbgValue of PHI nodes where the use follows dbg.value ↵Devang Patel2011-01-251-1/+3
| | | | | | intrinisic. llvm-svn: 124203
* This assertion is too restrictive, it does not apply for dangling dbg value ↵Devang Patel2011-01-251-8/+0
| | | | | | nodes (nodes where dbg.value intrinsic preceds use of the value). llvm-svn: 124202
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