| Commit message (Collapse) | Author | Age | Files | Lines |
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value. Adjust other code to deal with that correctly. Make
DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT take advantage of
this new flexibility to simplify the code and make it deal with unusual
vectors (like <4 x i1>) correctly. Fixes PR3037.
llvm-svn: 75176
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llvm-svn: 75161
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llvm-svn: 75160
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shortly to provide nicely printed comments and other goodies in
asm files.
llvm-svn: 75156
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llvm-svn: 75153
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registers based on dynamic conditions. For example, X86 EBP/RBP, when used as
frame register has to be spilled in the first fixed object. It should inform
PEI this so it doesn't get allocated another stack object. Also, it should not
be spilled as other callee-saved registers but rather its spilling and restoring
are being handled by emitPrologue and emitEpilogue. Avoid spilling it twice.
llvm-svn: 75116
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as an (index,bool) pair. The bool flag records whether the kill is a
PHI kill or not. This code will be used to enable splitting of live
intervals containing PHI-kills.
A slight change to live interval weights introduced an extra spill
into lsr-code-insertion (outside the critical sections). The test
condition has been updated to reflect this.
llvm-svn: 75097
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nodes with operand types that differ from the result type. (This
doesn't normally happen right now, because
SelectionDAGLowering::visitShuffleVector normalizes vector shuffles.)
llvm-svn: 75081
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llvm-svn: 75067
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number of elements. Make some simplifications based
on this (in particular SplitVecRes_SETCC). Tighten
up some checking while there.
llvm-svn: 75050
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llvm-svn: 75046
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llvm-svn: 75040
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module is required.
llvm-svn: 75025
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and cases alphabetically. No functionality change.
llvm-svn: 75001
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these instructions, no autoupgrade or backwards compatibility support is
provided.
llvm-svn: 74991
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llvm-svn: 74985
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VSETCC must define all bits, which is different than it was documented
to before. Since all targets that implement VSETCC already have this
behavior, and we don't optimize based on this, just change the
documentation. We now get nice code for vec_compare.ll
llvm-svn: 74978
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for now, conservatively return false.
llvm-svn: 74969
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as "X" constraint and "P" modifier on x86. Make this work.
(Change may not be sufficient to fix it for non-Darwin, but
I'm pretty sure it won't break anything.)
gcc.apple/asm-block-32.c
gcc.apple/asm-block-33.c
llvm-svn: 74967
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the input is legal (4 x i32)
llvm-svn: 74964
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llvm-svn: 74962
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finishes off enough support for vector compares to get the icmp/fcmp
version of 2008-07-23-VSetCC.ll passing.
llvm-svn: 74961
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(vector of bool).
llvm-svn: 74960
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eliminate the former.
llvm-svn: 74959
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llvm-svn: 74957
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llvm-svn: 74953
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llvm-svn: 74949
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llvm-svn: 74931
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llvm-svn: 74925
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previous cmp; a copy can not be inserted here if the copy insn also has
side effects. We don't have access to the attributes of copy insn here;
so just play safe by finding a safe locations for branch terminators.
llvm-svn: 74898
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llvm-svn: 74857
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llvm-svn: 74825
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llvm-svn: 74821
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spaces, shrink down includes and move some methods out-of-line
llvm-svn: 74817
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llvm-svn: 74814
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cleanup, removed some #includes and moved Object Code Emitter out-of-line.
llvm-svn: 74813
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llvm-svn: 74807
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arguments in a vararg call.
With the SVR4 ABI on PowerPC, vector arguments for vararg calls are passed differently depending on whether they are a fixed or a variable argument. Variable vector arguments always go into memory, fixed vector arguments are put
into vector registers. If there are no free vector registers available, fixed vector arguments are put on the stack.
The NumFixedArgs attribute allows to decide for an argument in a vararg call whether it belongs to the fixed or variable portion of the parameter list.
llvm-svn: 74764
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llvm-svn: 74760
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llvm-svn: 74733
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llvm-svn: 74720
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llvm-svn: 74718
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alignment method
llvm-svn: 74686
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llvm-svn: 74677
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llvm-svn: 74673
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llvm-svn: 74659
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llvm-svn: 74625
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defines any register. Also teaches the default commuteInstruction() to commute instruction without definitions (e.g. X86::test / ARM::tsp).
llvm-svn: 74602
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liveintervalanalysis and coalescer handling of implicit_def.
Note, isUndef marker must be placed even on implicit_def def operand or else the scavenger will not ignore it. This is necessary because -O0 path does not use liveintervalanalysis, it treats implicit_def just like any other def.
llvm-svn: 74601
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the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.
llvm-svn: 74580
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